Memory Concurrency Testing

Concept

Memory Concurrency Testing is described as a future TestRIG capability for memory-model testing. The proposed approach injects RVFI-DII instruction streams, annotated with specified timestamps, into multiple shared-memory cores to stimulate concurrency behavior and then checks traces against higher-level memory-model semantics.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Memory Concurrency Testing is presented in the TestRIG work as a future testing capability for memory-model testing. The source specifically states that TestRIG should support memory-model testing as part of its future development direction. TestRIG is described as an open-source RISC-V testing framework effort that aims to simplify verification through instrumentation of open implementations. [c1]

Proposed mechanism

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

TestRIG ← uses 70% 2e

Future work plans for TestRIG include memory concurrency testing.

TestRIG ← mentions 90% 2e

The paper discusses future memory concurrency testing capabilities for TestRIG.

Axe ← implements 90% 1e

Axe is used as a consistency checker for memory subsystem traces, relevant to memory concurrency testing.

TestRIG compares with → 80% 1e

TestRIG is described as needing to support memory concurrency testing in future work.

Axe ← uses 90% 1e

Axe is used for testing memory subsystem traces against higher-level memory-model semantics.

LINKED ENTITIES

1 links

TestRIG USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] c1: Memory Concurrency Testing is identified as a future TestRIG capability for memory-model testing, and TestRIG is positioned as an open-source RISC-V verification framework effort. Randomized Testing of RISC-V CPUs using Direct

[2] c2: The proposed mechanism injects timestamped RVFI-DII instruction streams into multiple shared-memory cores to stimulate concurrency behaviors. Randomized Testing of RISC-V CPUs using Direct

[3] c3: Memory Concurrency Testing would require a more advanced verification engine that checks RVFI traces for equivalence and against higher-level memory-model semantics, with Axe referenced as an example. Randomized Testing of RISC-V CPUs using Direct

[4] c4: TestRIG-compatible implementations and verification engines are collected in an open-source repository, and the authors expect TestRIG to lead toward a standardized testing framework for RISC-V. Randomized Testing of RISC-V CPUs using Direct