Memory Concurrency Testing Wiki

Memory Concurrency Testing

Concept WIKI v1 · 5/27/2026

Memory Concurrency Testing is described as a future TestRIG capability for memory-model testing. The proposed approach injects RVFI-DII instruction streams, annotated with specified timestamps, into multiple shared-memory cores to stimulate concurrency behavior and then checks traces against higher-level memory-model semantics.

Overview

Memory Concurrency Testing is presented in the TestRIG work as a future testing capability for memory-model testing. The source specifically states that TestRIG should support memory-model testing as part of its future development direction. TestRIG is described as an open-source RISC-V testing framework effort that aims to simplify verification through instrumentation of open implementations. [c1]

Proposed mechanism

The proposed mechanism is to inject RVFI-DII instruction streams with specified timestamps into multiple cores that share memory. According to the evidence, this should allow precise stimulation of concurrency behaviors. [c2]

Verification requirements

The evidence states that this capability would require a more advanced verification engine. Such an engine would need to test RVFI traces not only for equivalence, but also against higher-level memory-model semantics, with Axe cited in the source as an example. [c3]

Role in TestRIG

Memory Concurrency Testing is listed under the "Future of TestRIG" discussion. In that same context, the source notes that TestRIG-compatible implementations and verification engines have been collected in an open-source TestRIG repository, and that TestRIG is expected to contribute toward a standardized RISC-V testing framework. [c4]

LINKED ENTITIES

1 links

TestRIG USES

CITATIONS

4 sources

4 citations

[1] c1: Memory Concurrency Testing is identified as a future TestRIG capability for memory-model testing, and TestRIG is positioned as an open-source RISC-V verification framework effort. Randomized Testing of RISC-V CPUs using Direct

[2] c2: The proposed mechanism injects timestamped RVFI-DII instruction streams into multiple shared-memory cores to stimulate concurrency behaviors. Randomized Testing of RISC-V CPUs using Direct

[3] c3: Memory Concurrency Testing would require a more advanced verification engine that checks RVFI traces for equivalence and against higher-level memory-model semantics, with Axe referenced as an example. Randomized Testing of RISC-V CPUs using Direct

[4] c4: TestRIG-compatible implementations and verification engines are collected in an open-source repository, and the authors expect TestRIG to lead toward a standardized testing framework for RISC-V. Randomized Testing of RISC-V CPUs using Direct