Overview

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging is a processor-verification paper whose available evidence centers on Coverage-guided Aging and an endless randomized instruction-stream approach. The paper reports that Coverage-guided Aging complements other verification inputs by closing gaps and producing more balanced verification results.

Technical approach

The approach is described, in a later cross-level processor-verification comparison, as using a custom instruction stream generator to generate a single endless instruction stream. That comparison also characterizes the setup as highly architecture-specific and requiring significant manual effort to support different configurations.

In that comparison, the endless-stream approach is contrasted with a coverage-guided fuzzing setup that generates test cases one after another. The comparison states that the latter design simplifies co-simulation and makes it easier to test different core configurations, while still supporting arbitrary control flows, including self-loops, and load/store instructions. This comparison is useful for understanding the tradeoff: the paper's endless-stream method is positioned as a cross-level processor-verification technique, but later work highlights setup complexity around the custom stream generator.

Reported result: detected pipeline-related issue

The paper reports that, during development of the Coverage-guided Aging test generator, the authors discovered a micro-architectural related bug in the test-bench adapter accompanying an already well-tested industrial RTL core. The relevant section is titled Detected Pipeline Bug, indicating the issue was discussed in the context of pipeline behavior.

Verification context

The paper's references place it in the RISC-V verification ecosystem. The available reference list excerpt mentions RISC-V ISA tests, the RISC-V compliance task group, RISC-V CSR compliance testing, the RISC-V formal verification framework, and the OneSpin 360 DV RISC-V Verification App. The same excerpt also cites prior work on verifying instruction set simulators using coverage-guided fuzzing.