Micro-architectural Bug Detection

Concept

Micro-architectural bug detection concerns finding processor implementation bugs that arise from details such as pipelines, prefetching, fetch-buffering, and test-bench interaction. In the provided evidence, it is discussed through a RISC-V cross-level processor verification approach using endless randomized instruction streams and Coverage-guided Aging, which exposed an intricate bug in a heavily tested industrial processor.

First seen 5/30/2026

Last seen 5/30/2026

Evidence 3 chunks

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Overview

Micro-architectural bug detection is illustrated in the provided evidence as part of processor verification at the RTL/core-implementation level. The cited approach uses cross-level processor verification based on endless randomized instruction stream generation, with Coverage-guided Aging used to improve the distribution of exercised coverage points. The paper reports that this method achieved a more regular coverage distribution and found an intricate micro-architecture-related bug in an already heavily tested industrial processor and its accompanying test-bench infrastructure.

Verification setting

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 95% 3e

The paper detects micro-architectural bugs in the RTL processor.

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

CITATIONS

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[1] The cited cross-level processor verification approach uses endless randomized instruction stream generation and Coverage-guided Aging. Cross-Level Processor Verification via

[2] The approach initializes separate instruction generators with the same cryptographic seeds so they provide the same endless randomized instruction stream. Cross-Level Processor Verification via

[3] The RTL side of the flow must account for micro-architectural details such as pipelining, prefetching, and fetch-buffering through a core adapter. Cross-Level Processor Verification via

[4] Coverage-guided Aging produced a more regular coverage distribution and helped find an intricate micro-architecture-related bug in a heavily tested industrial processor. Cross-Level Processor Verification via

[5] The detected bug was triggered when the pipeline was only emptied by the test-bench adapter after valid instruction execution, allowing too many successive invalid instructions to leave the core without further instructions. Cross-Level Processor Verification via

[6] The paper identifies future work on advanced micro-architecture coverage metrics, including metrics for pipeline hazard handling. Cross-Level Processor Verification via

[7] The evidence contrasts the approach with other processor verification test-generation techniques such as model-based generation, machine-learning-guided generation, fuzzing, and symbolic execution, noting limitations for RTL verification or instruction-stream restrictions. Cross-Level Processor Verification via