Instruction-Injector

Tool

Instruction-Injector is a tool component in a cross-level RISC-V processor verification flow. It injects instruction sequences into randomized instruction generators while preserving generator-state consistency, so the RTL core and ISS reference streams remain comparable.

First seen 5/29/2026

Last seen 6/2/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

Instruction-Injector is a component of a cross-level processor verification setup for randomized, coverage-guided instruction stream generation. In the described flow, endless instruction streams are generated for co-simulation of an RTL core against an Instruction Set Simulator (ISS) reference model, with runtime coverage information used to guide generation. The architecture includes an Instruction-Injector and a Coverage-Observer between the instruction generators and the compared RTL/ISS executions.

Purpose

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RELATIONSHIPS

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 8e

The paper uses the Instruction-Injector to inject targeted instructions based on coverage hints.

Coverage-guided Aging uses → 100% 3e

Instruction-Injector uses hints from Coverage-Observer to inject instructions

Instruction Injection implements → 100% 2e

Instruction-Injector implements instruction injection into the random test generators.

InstrGen uses → 90% 1e

Instruction-Injector injects instruction sequences into InstrGen generators

LINKED ENTITIES

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship

Coverage-guided Aging USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] The verification approach uses randomized, coverage-guided endless instruction streams with an ISS reference model in co-simulation with an RTL core. Cross-Level Processor Verification via

[2] Instruction-Injector injects instruction sequences into random test generators while complying with their internal state. Cross-Level Processor Verification via

[3] Ignoring generator internal state during injection can produce differing instruction streams and cause a false Comparator result. Cross-Level Processor Verification via

[4] Legal injection is achieved by measuring the executed-instruction count before the current generator state and scheduling injection for the same near-future instruction count across all instruction generators. Cross-Level Processor Verification via

[5] The scheduling approach relies on deterministic random sources initialized with the same cryptographic seed producing the same random sequences. Cross-Level Processor Verification via

[6] The Coverage-Observer provides the Instruction-Injector with a random instruction sequence needed to cover a coverage point when a Coverage-guided Aging counter reaches its minimum limit. Cross-Level Processor Verification via