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Instruction-Injector

Tool WIKI v1 · 5/30/2026

Instruction-Injector is a tool component in a cross-level RISC-V processor verification flow. It injects instruction sequences into randomized instruction generators while preserving generator-state consistency, so the RTL core and ISS reference streams remain comparable.

Overview

Instruction-Injector is a component of a cross-level processor verification setup for randomized, coverage-guided instruction stream generation. In the described flow, endless instruction streams are generated for co-simulation of an RTL core against an Instruction Set Simulator (ISS) reference model, with runtime coverage information used to guide generation. The architecture includes an Instruction-Injector and a Coverage-Observer between the instruction generators and the compared RTL/ISS executions.

Purpose

The Instruction-Injector injects instruction sequences into random test generators while staying compliant with each generator's internal state. This state awareness is necessary because injecting without regard to internal generator state can make the generators produce different instruction streams, which may lead to a false Comparator result.

Operation

The tool supports legal injection by measuring how many instructions have executed before the current random-generator state is reached. It then schedules the injection for the same near-future instruction count across all instruction generators. The paper states that this is valid because deterministic random sources initialized with the same cryptographic seed provide the same random sequences.

Interaction with Coverage-guided Aging

Instruction-Injector is used together with the Coverage-Observer in the Coverage-guided Aging extension. The Coverage-Observer samples executed instructions, maps them to coverage points, and maintains aging counters. When a counter reaches its minimum limit, the Coverage-Observer gives the Instruction-Injector a hint: a random instruction sequence needed to cover the relevant coverage point. The sequence is built from instructions dynamically sampled during the run.

Context in verification flow

The overall verification approach targets broad and deep randomized testing by generating endless, unrestricted instruction streams that evolve at runtime based on observed coverage. The setup uses an ISS as a reference model in tight co-simulation with an RTL core. Within this context, the Instruction-Injector is the mechanism that inserts coverage-motivated instruction sequences without breaking synchronization between the generated streams.

LINKED ENTITIES

2 links
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES
Coverage-guided Aging USES

CITATIONS

6 sources
6 citations
[1] The verification approach uses randomized, coverage-guided endless instruction streams with an ISS reference model in co-simulation with an RTL core. Cross-Level Processor Verification via
[2] Instruction-Injector injects instruction sequences into random test generators while complying with their internal state. Cross-Level Processor Verification via
[3] Ignoring generator internal state during injection can produce differing instruction streams and cause a false Comparator result. Cross-Level Processor Verification via
[4] Legal injection is achieved by measuring the executed-instruction count before the current generator state and scheduling injection for the same near-future instruction count across all instruction generators. Cross-Level Processor Verification via
[5] The scheduling approach relies on deterministic random sources initialized with the same cryptographic seed producing the same random sequences. Cross-Level Processor Verification via
[6] The Coverage-Observer provides the Instruction-Injector with a random instruction sequence needed to cover a coverage point when a Coverage-guided Aging counter reaches its minimum limit. Cross-Level Processor Verification via