2026-06-13
5 items 220 entities 223 connections
Processed 24 entities and 27 relations.
Fuzzilicon CPU Instruction Set Architecture microarchitecture microcode x86 hardware fuzzing pre-silicon fuzzing post-silicon fuzzing formal verification runtime detection information flow tracking coverage-guided fuzzing RTL Red-Unlock mode microcode patching microarchitectural introspection reverse engineering bare-metal hypervisor-based fuzzing framework serialization oracle device under test performance counters Intel AMD
DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
source →Processed 78 entities and 74 relations.
DejaVuzz Dynamic Swappable Memory Differential Information Flow Tracking Hardware Dynamic Information Flow Tracking Processor Fuzzing Transient Execution Vulnerability Detection Training Derivation Strategy Training Reduction Strategy Taint Coverage Matrix Taint Liveness Annotation Differential Testing RTL Simulation Random Instruction Generation Template-Based Instruction Generation Control Flow Over-Tainting Mitigation Constant Time Execution Analysis Formal Verification SpecDoctor IntroSpectre TEESec CellIFT Synopsys VCS Yosys ISA Simulator Transient Execution Transient Window Microarchitectural Controllability Microarchitectural Observability Address Space Conflict Taint Propagation Side Channel Spectre-V1 Spectre-V2 Spectre-RSB Foreshadow Microarchitectural Data Sampling Branch Target Buffer Return Stack Buffer Reorder Buffer Load Fill Buffer Pre-Silicon Testing Register Transfer Level Stimulus Generation Instruction Sequence Generation Fuzzing Coverage Secret Encoding Design Under Test Swappable Region Transient Packet Trigger Training Packet Window Training Packet Swap Schedule Mux Toggle Coverage Control Register Coverage Hardware Behavior Coverage RISC-V BOOM XiangShan Shadow Circuit Control Flow Over-Tainting False Positive Reduction DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing Jinyan Xu Yangye Zhou Xingzhi Zhang Yinshuai Li Qinhan Tan Yinqian Zhang Yajin Zhou Rui Chang Wenbo Shen Zhejiang University Southern University of Science and Technology Princeton University DejaVuzz Source Code Chisel Transient Execution Vulnerability Detection Window Training Packet
Processed 56 entities and 55 relations.
Test Program Generator Architecture Verification Program Implementation Verification Program Architecture-Independent Generator Declarative Architectural Specification Instruction Tree Semantic Entity Generation Function Validation Function Object-Oriented Database Architecture Simulator Behavioral Simulator Hardware Simulator Constraint Solver Resource Manager Backtracking Address Expression Length Expression Data Expression Verification Task CISC Architecture RISC Architecture Random Test Program Generation Depth-First Tree Traversal Processor Verification Testing Knowledge Base Instruction Set Architecture Hardware Description Language VHDL Register Allocation Policy Memory Allocation Policy Operand Sub-Operand Condition Code Pipeline Mechanism Cache Mechanism Address Translation Floating Point Unit Data Type ISPS Memory Declaration Semantic Procedure Generate-and-Test Strategy User Interface Extractor Program ADD WORD Instruction MOVE CHARACTER LONG Instruction International Business Machines Corporation IBM AS/400 Processor IBM System/390 Processor Carry Look-Ahead Adder Instruction Instance Format Resource Overlap Page Fault Test Generator Implementation in C ANSI/IEEE Standard for Binary Floating Point Arithmetic
Processed 48 entities and 53 relations.
Genesys Automatic Workload Generation Synthetic Benchmark Generation Instruction Mix (IMIX) Instruction Level Parallelism (ILP) Branch Transition Rate (BTR) Branch Misprediction Rate Instruction Cache Miss Rate (ICMR) Data Cache Miss Rate Spatial Locality Temporal Locality Data Footprint Average Basic Block Size Dependency Distance SpreadRatio Convex Hull Program State-Space Coverage Machine Learning Based Performance Prediction Machine Learning Based Power Prediction Ridge Regression Principal Component Analysis (PCA) KMeans Clustering Design Space Exploration Supervised Learning Hardware Performance Counters Instructions Per Cycle (IPC) Micro-benchmark Predictive Benchmarking Strided Memory Access Code Generator X86 Assembly Code Generation SPEC CPU2006 MiBench MediaBench TPC-H Linux perf tool Intel RAPL CVXOPT Minnespec Genesys: Automatically Generating Representative Training Sets for Predictive Benchmarking Reena Panda Lizy K. John Andreas Gerstlauer The University of Texas at Austin Intel Xeon E5-2430 v2 Instruction Count Workload Characterization Over-fitting Prevention
AVPGEN—A Test Generator for Architecture Verification for IEEE Transactions on VLSI Systems - IBM Research
source →Processed 14 entities and 14 relations.
AVPGEN Architecture Verification Program Symbolic Execution Constraint Solving Biased Random Test Generation Constraint-Based Initial Value Generation SIGL Symbolic Instruction Graph Language Processor Conformance Verification Test Template Symbolic Constraint Biasing Technique S/390 Processor AVPGEN: Architecture Verification Program Generation for Processor Conformance Testing