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Bare-Metal Hypervisor-Based Fuzzing Framework

Concept

A bare-metal, hypervisor-based fuzzing framework is an execution environment designed to safely and deterministically run fuzzing workloads directly on target hardware (without a host operating system), using hypervisor-style isolation and control to wrap the device under test (DUT) and continuously monitor its behavior.

First seen 6/13/2026
Last seen 6/13/2026
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Overview

A bare-metal hypervisor-based fuzzing framework is a specialized execution substrate for fuzzing that combines two design choices:

  1. Bare-metal execution — the fuzzer and its workload run directly on the target processor without an intervening general-purpose operating system, removing OS-induced nondeterminism and reducing the trusted code base that can interfere with crash detection.
  2. Hypervisor-based control — a thin virtualization layer is used to isolate the device under test (DUT), govern its environment (interrupts, memory, I/O), and continuously observe execution state.
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RELATIONSHIPS

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Fuzzilicon ← uses 97% 1e
Fuzzilicon builds a bare-metal, hypervisor-based fuzzing framework that isolates the device under test and monitors execution.
device under test uses → 92% 1e
The bare-metal hypervisor-based fuzzing framework isolates and controls the device under test.

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CITATIONS

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[1] Fuzzilicon builds a bare-metal, hypervisor-based fuzzing framework that isolates the device under test (DUT), controls its environment, and continuously monitors execution, in order to ensure safe and deterministic execution of fuzzing workloads on the target CPU. Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer - arXiv
[2] The framework is paired with a serialization oracle that synthesizes semantically equivalent variants of instruction sequences, improving fuzzing reproducibility and enabling reliable detection of vulnerabilities and divergences across microarchitectural implementations. Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer - arXiv
[3] Together with microcode instrumentation, these capabilities enable feedback-driven fuzzing of real, post-silicon x86 processors with microarchitectural visibility, uncovering rare execution paths and vulnerabilities, without requiring RTL access or specialized hardware. Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer - arXiv
[4] Implementation details of the framework, including μcode instrumentation and control infrastructure, are described in Section V of the paper. Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer - arXiv