2026-06-14
3 items 166 entities 216 connections
Processed 54 entities and 69 relations.
GoldenFuzz Golden Reference Model Device Under Test instruction block differential testing coverage-guided fuzzing hardware fuzzing RISC-V ISA Direct Preference Optimization Simple Preference Optimization Reinforcement Learning from Human Feedback intra-instruction semantics inter-instruction semantics block-wise test case generation preference pair fuzzing memory intra-test case scoring inter-test case scoring digital twin RTL FSM coverage condition coverage line coverage MUX toggle coverage RISC-V assembly instruction generation privilege mode transition Physical Memory Protection GPT-2 Generative Pre-trained Transformer Byte-Pair Encoding transformer architecture auto-regressive language model Spike RISC-V simulator Synopsys VCS RocketChip BOOM CVA6 Cascade ChatFuzz DifuzzRTL TheHuzz American Fuzzy Lop GoldenFuzz: Generative Golden Reference Hardware Fuzzing Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi Technical University of Darmstadt mismatch detection RISC-V instruction corpus test case validity endianness vulnerability interrupt delegation vulnerability
Processed 70 entities and 79 relations.
TheHuzz hardware fuzzing instruction fuzzing golden reference model comparison golden reference model random regression testing mutation-based fuzzing seed generation stimulus generation coverage metrics statement coverage branch coverage expression coverage toggle coverage condition coverage FSM coverage RTL hardware description language design under test illegal instruction generation opcode mutation bit-flip mutation feedback-guided fuzzing instruction-mutation pair optimization baremetal environment assembly-level instruction generation configuration instructions test instructions DifuzzRTL AFL RFUZZ Cadence JasperGold Synopsys VCS spike ISA emulator or1ksim CPLEX GCC toolchain ModelSim OSS-Fuzz Syzkaller Ariane processor mor1kx processor or1200 processor Rocket Core RISC-V OpenRISC ISA finite state machine floating wire signal transition hardware vulnerability detection formal verification information flow tracking hardware common weakness enumeration FENCE.I instruction cache coherency instruction decoder multiplexer register file arithmetic logic unit Rahul Kande Addison Crump Garrett Persyn Patrick Jauernig Ahmad-Reza Sadeghi Aakash Tyagi Jeyavijayan Rajendran Texas A&M University Technische Universität Darmstadt TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities feedback-guided fuzzing
Processed 42 entities and 68 relations.
Cascade Asymmetric ISA Pre-Simulation CPU Fuzzing Differential Fuzzing Program Reduction Control Flow Entanglement with Data Flow Intermediate Program Construction RISC-V ISA Program Completion Rate Fuzzing Instruction Prevalence RTL Simulation Control Register Coverage Multiplexer Select Coverage Simulator-Based Coverage Basic Block cf-ambiguous Instructions Instruction Set Simulator Bug-Triggered Program Non-Termination Dependency Chain Length Privilege Transitions FPU Operations Control and Status Registers Memory Management in Program Generation Offset Register Construction DifuzzRTL TheHuzz RFUZZ Spike ISS Yosys HypFuzz Cascade: CPU Fuzzing via Intricate Program Generation Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich VexRiscv PicoRV32 Kronos CVA6 Rocket Core BOOM Cascade Python Implementation