Computation and information processing form the backbone of modern society, and their security fundamentally depends on the trustworthiness of the underlying hardware. At the core of secure computing are CPUs, which are expected to faithfully implement their Instruction Set Architectures and enforce strict isolation between processes. However, this assumption has been increasingly challenged by the discovery of critical architectural and microarchitectural-level vulnerabilities [1, 2, 3, 4]. These attacks demonstrate that flaws in CPU microarchitectural can be exploited to leak data, bypass protections, or undermine system integrity, even for secure and well-written software [5]. Indeed, modern processors, particularly in the x86 family, are highly complex, with layers of undocumented behavior implemented in proprietary μ\mucode [6]. As designs become increasingly complex and opaque, the risk of hardware-level security flaws continues to grow [7].

To detect hardware-level vulnerabilities, researchers have traditionally relied on techniques such as formal verification [8, 9, 10, 11, 12], runtime detection [13, 14], information flow tracking [15, 16, 17], and hardware fuzzing [18, 19]. Among them, hardware fuzzing has emerged as a promising approach due to its scalability and adaptability to various designs [20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41]. Hardware fuzzing has evolved into two distinct approaches: pre-silicon fuzzing, which targets Register-Transfer Level (RTL) models during hardware development, and post-silicon fuzzing, which evaluates manufactured processors under real execution conditions [20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41]. While pre-silicon fuzzing is widely studied in literature thanks to the deep observability and fine-grained instrumentation within the RTL model [20, 21, 25, 26, 27, 28, 29, 30, 33, 39, 40, 41], post-silicon fuzzing is rarely touched. The reason is straightforward: post-silicon fuzzers commonly target black-box or proprietary CPUs (e.g., from Intel and AMD) with visibility limited to architectural registers or crash symptoms [24]. Even worse, the internal microarchitectural state and μ\mucode-level behavior, where many subtle bugs manifest [1, 42, 2], are largely inaccessible and undocumented. Existing hardware feedback mechanisms, such as performance counters or architectural registers, offer only coarse-grained or indirect insight. The lack of transparency and informative feedback prevents the evaluator from finding unexpected behaviors and tracing corresponding root causes.

Our Contribution. In this work, we present Fuzzilicon, the first post-silicon fuzzer for proprietary x86 CPUs with gray-box visibility. Fuzzilicon introduces a novel internal microarchitectural feedback channel to guide test generation. By running the CPU in a Red-unlocked mode [43] and leveraging undocumented debugging and instrumentation capabilities in Intel processors [44], we gain access to the μ\mucode engine interface. We re-purpose this interface, which is typically used to deploy μ\mucode patches, as a programmable introspection layer, inserting lightweight instrumentation directly into the processor. Through careful reverse engineering, we construct μ\mucode patches that instrument internal μ\mucode execution paths. This turns a proprietary CPU into a gray box, enabling observation of internal execution states (e.g., μ\mucode path transitions) at runtime, without RTL access or specialized hardware. To ensure safe and deterministic execution of fuzzing workloads on the target CPU, we build a bare-metal, hypervisor-based fuzzing framework that isolates the device under test (DUT), controls its environment, and continuously monitors execution. We further introduce a serialization oracle that synthesizes semantically equivalent variants of instruction sequences, improving fuzzing reproducibility and enabling reliable detection of vulnerabilities and divergences across microarchitectural implementations. Together, these capabilities enable feedback-driven fuzzing of real, post-silicon x86 processors with microarchitectural visibility, uncovering rare execution paths and vulnerabilities.

The rest of this paper is organized as follows. Section II provides background on key concepts necessary for understanding Fuzzilicon, including x86 μ\mucode execution, instruction decoding, Red-Unlock mode, and microarchitectural introspection techniques. Section III details the core technical challenges of applying coverage-guided fuzzing to commercial x86 CPUs. Section IV outlines the design of Fuzzilicon, while Section V describes its framework implementation, including μ\mucode instrumentation and control infrastructure. Section VI evaluates Fuzzilicon’s effectiveness in terms of discovered vulnerabilities, coverage, and performance. Section VII discusses the Fuzzilicon with more insights. Section VIII discusses related works. Section IX concludes this work.