Biasing Technique

Concept

In processor architecture verification, a biasing technique is a method used to steer automated test generation toward conditions that are likely to expose design bugs. Biasing techniques are a core ingredient of the AVPGEN test generator, where they are combined with symbolic execution, constraint solving, and user-specified SIGL templates to focus tests on architecturally interesting states.

First seen 6/13/2026

Last seen 6/13/2026

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Overview

In the context of processor architecture verification, a biasing technique (also referred to as a biasing function) is a mechanism used to direct an automated test generator away from uniform random exploration and toward conditions that are more likely to reveal bugs in a processor implementation. Biasing techniques are typically used together with symbolic execution and constraint solving, so that selection of instructions, operands, and intermediate values can be weighted toward architecturally interesting cases.

Biasing Techniques in AVPGEN

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AVPGEN ← uses 100% 1e

AVPGEN uses various biasing techniques to focus tests on conditions likely to activate bugs.

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CITATIONS

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[1] AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques, to generate effective tests. AVPGEN—A Test Generator for Architecture Verification for IEEE Transactions on VLSI Systems - IBM Research

[2] Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. AVPGEN—A Test Generator for Architecture Verification for IEEE Transactions on VLSI Systems - IBM Research

[3] A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. AVPGEN—A Test Generator for Architecture Verification for IEEE Transactions on VLSI Systems - IBM Research

[4] The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. AVPGEN—A Test Generator for Architecture Verification for IEEE Transactions on VLSI Systems - IBM Research

[5] AVPGEN and its biasing techniques have been used successfully to debug many S/390 processors and are an integral part of the design process for these processors. AVPGEN—A Test Generator for Architecture Verification for IEEE Transactions on VLSI Systems - IBM Research

[6] In low-power CMOS design, reverse back-gate biasing is a distinct technique that can dramatically reduce standby leakage (e.g., reducing standby power to 2.64 nW in a 65-nm SOTB BIC chip). A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB