Overview
In the context of processor architecture verification, a biasing technique (also referred to as a biasing function) is a mechanism used to direct an automated test generator away from uniform random exploration and toward conditions that are more likely to reveal bugs in a processor implementation. Biasing techniques are typically used together with symbolic execution and constraint solving, so that selection of instructions, operands, and intermediate values can be weighted toward architecturally interesting cases.
Biasing Techniques in AVPGEN
The IBM AVPGEN system, described in AVPGEN—A Test Generator for Architecture Verification (IEEE Transactions on VLSI Systems), generates architecture verification programs (AVPs) to check the conformance of processor designs to a specified architecture. To produce effective tests, AVPGEN combines several techniques:
- Symbolic execution of instruction sequences.
- Constraint solving to determine operand and state values that satisfy template constraints.
- Biasing techniques / biasing functions that weight the selection of values and instructions toward architecturally interesting cases.
Rather than relying on purely random—or merely biased random—choices, AVPGEN often selects intermediate or final values for the generated program and then solves for initial register/memory values that lead the processor into those targets. Users express their intent through templates written in the SIGL (Symbolic Instruction Graph Language) template language, and the combination of these user-specified symbolic constraints with the biasing functions is what focuses the generated tests on conditions likely to activate various kinds of bugs.
Distinction from Earlier Random Approaches
Many earlier architecture-verification systems applied biasing only at the level of making biased random choices during generation. AVPGEN's approach differs in two ways:
- Biasing is applied together with symbolic constraint solving over SIGL templates, rather than purely over concrete random draws.
- Because constraints are solved symbolically, biasing can target intermediate or final architectural states of a test, and the generator works backwards to compute initial values that reach those states.
Industrial Use
AVPGEN and its biasing techniques have been used to debug many IBM S/390 processors and have been an integral part of the design process for these processors.
Related Hardware Meaning: Body / Back-Gate Biasing
The phrase biasing technique is also used in low-power circuit design to refer to transistor-level techniques such as reverse back-gate (body) biasing, which modulates the threshold voltage of MOS devices to cut leakage. For example, a 65-nm SOTB CMOS bitmap index creation core applied a reverse back-gate biasing technique in standby mode, reducing standby power to 2.64 nW. This hardware usage is conceptually unrelated to verification-level biasing techniques, but the terminology overlaps in the EDA literature; the two meanings should not be conflated.