AMD

Organization

AMD is represented in the provided evidence through an AMD-authored technical article on microcode-stimulus generation for microprocessor verification. The article describes a constrained-random SystemVerilog methodology using the Synopsys VCS constraint solver, contrasting a single-class opcode model with a hierarchical multi-class approach intended to reduce memory requirements and improve generation performance.

First seen 5/26/2026

Last seen 6/13/2026

Evidence 4 chunks

Wiki v1

WIKI

Technical context

The provided evidence documents AMD in the context of microprocessor verification methodology. In the article “Generating AMD microcode stimuli using VCS constraint solver,” Gregory Tang and Rajat Bahl are identified as authors from AMD, Inc., alongside Alex Wakefield and Padmaraj Ramachandran from Synopsys Inc. [C1]

Microcode-stimulus generation

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NEIGHBORHOOD

3 nodes · 2 edges

graph · AMD · depth=1

RELATIONSHIPS

5 connections

Synopsys VCS uses → 90% 3e

AMD uses Synopsys VCS as the constraint solver in their verification flow.

Hierarchical Constrained-Random Test Generation uses → 1e

AMD uses hierarchical constrained-random test generation in its CPU verification flow.

hierarchical constrained-random stimulus generation uses → 88% 1e

AMD researchers developed and use the hierarchical constrained-random stimulus generation approach.

John Kalamatianos ← part of 95% 1e

John Kalamatianos is an industry mentor at AMD

microcode implements → 85% 1e

AMD produces black-box or proprietary CPUs with microcode-level behavior that is inaccessible.

LINKED ENTITIES

1 links

Synopsys Inc. coauthored_article_with The evidence identifies AMD authors Gregory Tang and Rajat Bahl and Synopsys Inc. authors Alex Wakefield and Padmaraj Ramachandran on the same technical article.

CITATIONS

7 sources

7 citations — click to expand

[1] C1: Article authorship identifies Gregory Tang and Rajat Bahl as AMD, Inc. authors and Alex Wakefield and Padmaraj Ramachandran as Synopsys Inc. authors. Generating AMD microcode stimuli using VCS constraint solver

[2] C2: The article states that increasing microprocessor-design complexity has reduced hand-written directed tests and encouraged automated random test generators for microcode sequences. Generating AMD microcode stimuli using VCS constraint solver

[3] C3: The described approach uses a hierarchical constrained-random method with the Synopsys VCS constraint solver to improve generation speed, memory use, distribution, and corner-case biasing. Generating AMD microcode stimuli using VCS constraint solver

[4] C4: SystemVerilog constraints are described as a concise way to model instruction attributes and distributions, and an initial single-class prototype held constraints for all opcodes. Generating AMD microcode stimuli using VCS constraint solver

[5] C5: The opcode generator architecture has an upper SystemVerilog random-sequence layer with weighted knobs and a lower opcode-class layer randomized with constraints and weights. Generating AMD microcode stimuli using VCS constraint solver

[6] C6: The single-class opcode model is flexible but can slow randomization; the cited class contained approximately 100 random variables and 800 constraint equations. Generating AMD microcode stimuli using VCS constraint solver

[7] C7: The article describes splitting opcode constraints into smaller hierarchical classes, using a base class plus subclasses, to reduce memory requirements and improve performance. Generating AMD microcode stimuli using VCS constraint solver