2026-06-25
4 items 66 entities 65 connections
Processed 22 entities and 30 relations.
ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers ProcessorFuzz CSR-transition coverage metric hardware fuzzing processor fuzzing CSR RTL HDL DIFUZZRTL Rocket BOOM BlackParrot RISC-V Boston University University of Washington Sadullah Canakci Chathura Rajapaksha Anoop Mysore Nataraja Leila Delshadtehrani Michael Taylor Manuel Egele Ajay Joshi
Processed 26 entities and 16 relations.
On a consistency testing model and strategy for revealing RISC processor's dark instructions and vulnerabilities Specification-based test program generation for MIPS64 memory management units Constrained random verification for RISC-V: Overview, evaluation and discussion Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging Towards specification and testing of RISC-V ISA compliance Open-source validation suite for RISC-V Data constraint generation technology for microprocessor instruction verification based on SMT solver Genesys-Pro: Innovations in test program generation for functional processor verification Enhancing the efficiency of Bayesian network based coverage directed test generation A reinforcement learning approach to directed test generation for shared memory verification Using a constraint satisfaction formulation and solution techniques for random test program generation Verifying instruction set simulators using coverage-guided fuzzing Constrained random verification Specification-based test program generation Randomized instruction stream generation Coverage-guided aging Data constraint generation Bayesian network-based coverage-directed test generation Reinforcement learning-based directed test generation Constraint satisfaction for random test program generation Coverage-guided fuzzing Genesys-Pro SMT solver Instruction set simulator RISC-V MIPS64
Processed 10 entities and 14 relations.
Processed 8 entities and 5 relations.