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STIMSMITH
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2026-06-26

4 items 54 entities 38 connections

Intelligent Graybox Fuzzing via ATPG-Guided Seed Generation and Submodule Analysis

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Processed 9 entities and 7 relations.

Fuzzing Hardware Fuzzing Coverage-Guided Graybox Fuzzing (CGF) RTL Fuzzing Directed Graybox Fuzzing (DGF) Directed Fuzzing DirectFuzz PROFUZZ Code Coverage

Day 21: CSRs, Traps & Exceptions — M-Mode Privilege in Verilog | RISC-V from Scratch

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Processed 14 entities and 2 relations.

RISC-V CSRRW CSRRS CSRRC ECALL MRET Trap handling flow tb_csr.v tb_csr.vcd $dumpfile $dumpvars Direct instantiation unit testbench Illegal instruction exception Misaligned address exception

Leakage Contracts for Processors with Transitions and Glitches

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Processed 29 entities and 28 relations.

Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches Johannes Haring Vedad Hadžić Roderick Bloem Graz University of Technology IAIK RISC-V Ibex RV32E RV32I Leakage contracts Glitch-aware leakage model Transition leakage Glitch leakage Value leakage Symbolic execution 2-safety hyperproperty verification Masking t-probing security Genoa MaskVerif scVerif Coco glitch-contracts leak step_cpu glitchy_decode regfile_glitches load_leakage

Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches | IACR Transactions on Cryptographic Hardware and Embedded Systems

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Processed 2 entities and 1 relations.

RISC-V Ibex