Data constraint generation

Technique

A verification technique that automatically derives data constraints for microprocessor instructions using an SMT solver, introduced by Tan et al. (2020) and subsequently applied in RISC-V test sequence generation workflows for functional processor verification.

First seen 6/25/2026

Last seen 6/25/2026

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Data constraint generation

Definition

Data constraint generation is a technique used in functional verification of microprocessors. It systematically produces the data constraints (e.g., relationships between source operands, immediate values, register states, and memory addresses) that an instruction sequence must satisfy in order to exercise a specific architectural scenario. By expressing these data preconditions as logical formulas and discharging them with an SMT (Satisfiability Modulo Theories) solver, the technique yields concrete, satisfiable operand values that can be plugged into a test program.

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Data constraint generation technology for microprocessor instruction verification based on SMT solver ← uses 90% 1e

Develops and employs data constraint generation for instruction verification.

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CITATIONS

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[1] Data constraint generation is a microprocessor instruction verification technique that uses an SMT solver to derive data constraints and concrete operand values. A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)

[2] The technique was introduced by Tan Jian, Luo Qiaoling, Wang Liyi et al. in Journal of Computer Research and Development, 2020, 57(12): 2694–2702, doi: 10.7544/issn1000-1239.2020.20190718. A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)

[3] Data constraint generation is used as a building block in RISC-V test sequence generation to provide operand data satisfying scenario-specific constraints. A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)

[4] The technique generalizes earlier constraint-satisfaction approaches to test program generation, such as Bin et al. (IBM Systems Journal, 2002) and the Genesys-Pro framework (Adir et al., 2004). A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)