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Data constraint generation

Technique WIKI v1 · 6/25/2026

A verification technique that automatically derives data constraints for microprocessor instructions using an SMT solver, introduced by Tan et al. (2020) and subsequently applied in RISC-V test sequence generation workflows for functional processor verification.

Data constraint generation

Definition

Data constraint generation is a technique used in functional verification of microprocessors. It systematically produces the data constraints (e.g., relationships between source operands, immediate values, register states, and memory addresses) that an instruction sequence must satisfy in order to exercise a specific architectural scenario. By expressing these data preconditions as logical formulas and discharging them with an SMT (Satisfiability Modulo Theories) solver, the technique yields concrete, satisfiable operand values that can be plugged into a test program.

Origin and primary reference

The technique was formalized in the paper:

  • TAN Jian, LUO Qiaoling, WANG Liyi, et al. "Data constraint generation technology for microprocessor instruction verification based on SMT solver," Journal of Computer Research and Development, 2020, 57(12): 2694–2702. doi: 10.7544/issn1000-1239.2020.20190718.

In this work, data constraints for instruction-level verification are encoded into SMT formulas; the SMT solver is then used both to decide satisfiability of the constraints and to produce concrete data assignments, eliminating the manual effort typically required to pick instruction operands that satisfy complex inter-instruction data dependencies.

Use in RISC-V test sequence generation

Data constraint generation is adopted as a building block in the RISC-V test sequence generation method published in the Journal of Electronics & Information Technology (doi: 10.11999/JEIT230480). That work cites Tan et al. (2020) as the reference for the underlying data-constraint formulation, and uses SMT-driven data assignment to feed generated instruction sequences with operand values that respect the verification scenario's data preconditions.

Relationship to related verification techniques

Data constraint generation sits within a broader family of constraint-driven test-program generation methods:

  • Constraint-satisfaction test generation. BIN E, EMEK R, SHUREK G, et al. "Using a constraint satisfaction formulation and solution techniques for random test program generation," IBM Systems Journal, 2002, 41(3): 386–402, established the use of constraint satisfaction formulations for random test program generation, which Tan et al. extend by leveraging SMT solvers for data constraint generation.
  • Genesys-Pro. ADIR A, ALMOG E, FOURNIER L, et al. "Genesys-Pro: Innovations in test program generation for functional processor verification," IEEE Design & Test of Computers, 2004, 21(2): 84–93, provides a related model-generator framework for functional processor verification against which data constraint generation can be contrasted.
  • Constrained random verification for RISC-V. AHMADI-POUR S, HERDT V, DRECHSLER R. "Constrained random verification for RISC-V: Overview, evaluation and discussion," MBMV 2021, and HERDT V, GROßE D, DRECHSLER R. "Closing the RISC-V compliance gap: Looking from the negative testing side," DAC 2020, supply the surrounding RISC-V compliance and constrained-random context in which data constraint generation is applied.
  • Specification-based test generation. KAMKIN A S and KOTSYNYAK A M. "Specification-based test program generation for MIPS64 memory management units," Proceedings of the Institute for System Programming of the RAS, 2016, 28(4): 99–114, is an earlier specification-driven approach that the SMT-based data-constraint technique generalizes.

Typical workflow

Based on the cited works, the data-constraint-generation workflow in microprocessor instruction verification is:

  1. Identify the verification scenario and the sequence of instructions required to exercise it.
  2. Encode the data preconditions of the scenario — including inter-instruction data dependencies, register/memory state requirements, and architectural corner cases — as SMT formulas.
  3. Invoke an SMT solver to check satisfiability and to extract concrete operand values that satisfy the formulas.
  4. Instantiate the instruction sequence with the solver-provided data to form a runnable test program.

This workflow is what enables subsequent works, such as the JEIT RISC-V test-sequence generation method, to produce instruction sequences whose operands are guaranteed to be consistent with the targeted verification scenario.

LINKED ENTITIES

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Data constraint generation technology for microprocessor instruction verification based on SMT solver USES

CITATIONS

4 sources
4 citations
[1] Data constraint generation is a microprocessor instruction verification technique that uses an SMT solver to derive data constraints and concrete operand values. A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)
[2] The technique was introduced by Tan Jian, Luo Qiaoling, Wang Liyi et al. in Journal of Computer Research and Development, 2020, 57(12): 2694–2702, doi: 10.7544/issn1000-1239.2020.20190718. A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)
[3] Data constraint generation is used as a building block in RISC-V test sequence generation to provide operand data satisfying scenario-specific constraints. A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)
[4] The technique generalizes earlier constraint-satisfaction approaches to test program generation, such as Bin et al. (IBM Systems Journal, 2002) and the Genesys-Pro framework (Adir et al., 2004). A RISC-V Test Sequences Generation Method Based on Instruction ... (JEIT)