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Comprehensive lockstep verification for NaxRiscv SoC integrating RISCV DV, RVLS, and Questa/UVM Billal Ighilahriz, Olivier Savry

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Billal Ighilahriz, Olivier Savry. Comprehensive lockstep verification for NaxRiscv SoC integrating RISCV DV, RVLS, and Questa/UVM. RISC-V Summit Europe, May 2025, Paris, France. ⟨cea-05052859⟩

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Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM Billal Ighilahriz and Olivier Savry

    Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble, France 1
    Email: firstname.name@cea.fr

    Abstract

This paper presents a robust lockstep verification framework for the NaxRiscv System-on-Chip (SoC) —a flexible, open-source, out-of-order, and superscalar RISC-V core. Our methodology integrates cycle-accurate RTL simulation using Verilator, functional co-simulation with the Spike golden model, and constrained-random test generation via RISCV-DV to achieve a comprehensive verification framework. Functional coverage metrics are collected through a Questa/UVM-based verification environment, enabling early detection of subtle behavioral mismatches and corner-case failures. Our methodology rigorously validates ISA compliance but also significantly enhancing the overall verification process.

                    Introduction                                  Set Architecture (ISA) and its extensions conform to the
Processor     verification   remains    one   of   the    most    specifications. These industry-recognized suites provide an
challenging phases in modern hardware design, especially          essential baseline by checking   both basic     ISA          and
given the       growing     complexity   of       contemporary    microarchitectural conformance.
architectures.  To ensure   robust  performance,      advanced
verification techniques and specialized tools are employed
to rigorously test designs and uncover hidden bugs. In our            Directed
framework for verifying RISC-V architectures, randomized              Simu OS     tests
execution scenarios are generated and detailed Register-              Boot
Transfer Level (RTL) simulation outputs are meticulously                                        Random
compared against those from a trusted reference model.                                          tests
         Our approach is built around a lockstep co-simulation
technique, where the Design Under Test (DUT) and a
golden Instruction Set Simulator (ISS) perform identical
operations in   parallel,  enabling     real-time  discrepancy        Functionally validated design
detection and efficient debugging. This methodology has
been applied to NaxRiscv [1]—a highly configurable, out-              Figure 1 : Multi-level verification strategy
of-order, and   superscalar core   supporting    multiple  ISA
extensions (including             RV32/64IMAFDC), it  supports      Following these  directed        tests,  the       methodology
operating systems like Linux and FreeRTOS and facilitates         incorporates the execution of real-world benchmarks to
rapid on-FPGA    prototyping      when  integrated   with  the    assess  performance and        software–hardware    integration.
LiTeX [2] framework. Developed using SpinalHDL [3]—               This phase involves running applications and performance¹
modern hardware design language uses           the Scala Build    metrics   such as CoreMark     and    Dhrystone, as     well  as
Tool (SBT) to build the project and simulate the execution        executing operating system boot sequences ranging from
of the core. Moreover,                                            FreeRTOS to the Linux boot stage.
                    Multi-level verification strategy                      To further stress the design and explore its functional
                                                                  boundaries, the strategy leverages RISCV-DV          [4], a tool
        The verification methodology is structured as a multi-    that automatically generates constrained-random assembly
layered approach that combines directed testing, real-world       programs. These tests deliberately target edge cases—such
benchmarking, and constrained-random testing to ensure a          as misaligned instructions, register dependencies (RD/RS),
comprehensive   evaluation    of   both     architectural  and    pipeline hazards, memory access violations, and unhandled
microarchitectural aspects  of   the  design.     The  process    interrupts—thereby probing complex execution paths. In
begins with an automated Jenkins Continuous Integration           parallel, a robust functional coverage model, based on
(CI) pipeline that executes standard compliance test suites       Universal Verification Methodology (UVM) and embedded
—specifically, riscv-tests and riscv-arch-tests—which serve
as established benchmarks for verifying that the Instruction      1 This  work was  funded thanks to  the French  national program
                                                                  ”Programme Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05

RISC-V Summit Europe, Paris, 12-15th May 2025                                                                                    1

       within RISCV-DV, ensures exhaustive validation of all ISA    (UCDB) file and finally transformed into a human-readable
      features, covering various opcodes, extensions (such as F,    report via the “vcover report” command. This detailed
    D, and C), and the proper interactions with system registers    coverage analysis provides metrics for each instruction
          (CSRs). This integrated approach guarantees that every    along with various coverpoints such as operand registers,
        aspect of the design is rigorously validated, from basic    branch outcomes, and memory alignment, ensuring that the

compliance to resilience under real-world conditions. verification process remains both exhaustive and precise Lockstep Verification Workflow A Jenkins-based CI pipeline automates regression testing and dynamically scales RISCV-DV test generation until Mt ars fa sion predefined coverage targets are met, providing rapid Gee feedback on design modifications. By seamlessly G DUT Waveot _ integrating RISCV-DV’s comprehensive test generation, Trace RVLS’s rigorous lockstep enforcement, and Questa/UVM’s moe ati pry Rus ry detailed coverage analysis, our framework effectively eliminates blind spots, guarantees strict ISA compliance, wm ain Spice and facilitates early bug detection—ultimately reinforcing eos the reliability of our NaxRiscv SoC implementations.

                                                                                          Results Overview
 Figure 2 : Lockstep RTL & ISS Verification Platform                                 Our experimental results clearly demonstrate that our
                                                                    SoC-level integrated lockstep verification framework can
 We   present   a    comprehensive    lockstep      verification    detect   critical     issues    that     conventional       core-level
      framework that integrates several advanced tools to ensure    simulations fail to detect. Initially, discrepancies in the

both functional and architectural compliance for the IO/memory mapping triggered ˝trap_store_access_fault˝ NaxRiscv SoC. At its core, RISCV-DV—a robust, open- events. In another instance, a misaligned instruction source framework developed by Google, coded in generated by RISCV-DV resulted in a malformed opcode, SystemVerilog/UVM, this generator of randomized introduce a mismatch between DUT and the ISS due to a instruction sequences and exhaustive test programs for the lack of verification of the Rd/Rs registers of certain RV32/64IMAFDC ISAs across multiple privilege modes compressed instructions (e.g., C.LWSP) in the DUT (M, S, and U), deliberately targeting critical edge cases to causing a ˝trap_load_page_fault˝ events. Additionally, maximize functional coverage. mismatches in the CSR configurations between the DUT These test programs are executed in SocSim, a Scala- and the golden reference Spike, led to observable execution based multi-core SoC simulator that leverages Verilator for anomalies (e.g., DUT missed a trap). These findings cycle-accurate RTL simulation and golden Instruction Set confirm that real-time cycle-by-cycle comparison and Simulator (ISS). The RTL simulation environment provides random generation of instruction sequences is essential to precise clock-cycle modeling and deep visibility into uncover subtle design issues, thereby enhancing overall internal signals (such as the program counter, Control and processor reliability. Status Registers (CSRs), and memory transactions), with Conclusion detailed Value Change Dump (VCD) outputs available for further analysis. The simulator’s outputs are rigorously compared against the functional emulation provided by This work presents a robust locking verification framework Spike—an open-source ISS that serves as our golden that bridges the critical gap between architectural reference by accurately managing CSR operations, general specifications and real-world operational integrity in the and floating-point registers, and critical extensions like NaxRiscv SoC. By integrating cycle-accurate simulation Compressed, Atomics, and the Floating-Point Unit (via Verilator), functional co-simulation (using Spike), To achieve real-time trace alignment, SocSim RISCV-DV-driven constrained random test generation, and incorporates the RISC-V Lock-Step (RVLS) framework Questa/UVM-powered coverage analysis—all via a Java Native Interface (JNI). This integration synchronized through RVLS’s real-time trace alignment— meticulously synchronizes instruction execution and the framework significantly enhances verification efficacy. asynchronous events (e.g., interrupts and exceptions) on a This cohesive approach not only ensures strict architectural cycle-by-cycle basis by comparing the DUT’s state with compliance but also enables early detection of even the that of Spike (Step & Compare). In parallel, comprehensive most elusive corner-case bugs, including memory access coverage metrics—including instruction, CSR, and branch integrity, interrupt handling, and exception management. —are extracted from the execution traces. The DUT’s With its rigorous and scalable methodology, this tracer.log and Spike’s spike.log are first converted to CSV framework strengthens confidence in the SoC’s functional format; then, using the Questa RTL simulator, the coverage correctness and resilience across diverse operational data is collected into a binary Unified Coverage Database scenarios.

2 RISC-V Summit Europe, Paris, 12-15th May 2025

 Références

[1] NaxRiscv—An Open-Source OoO Superscalar Softcore, Suisse: Available online: https://github.com/SpinalHDL/NaxRiscv, 2022. [2] F. Kermarrec, S. Bourdeauducq, H. Badier et J. Le Lann, «LiteX—An open-source SoC builder framework based on Migen Python DSL.,» arXiv, n° %12005.02506, 2020. [3] «SpinalHDL,» An Open-Source high-level HDL, 2014. [En ligne]. Available: https://github.com/SpinalHDL/SpinalHDL. [Accès le 2024]. [4] Google, «RISC-V DV,» 2019. [En ligne]. Available: https://github.com/google/riscv-dv. [Accès le 2024].

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