Concept
Concept
2130 entities#
1 escape bugs
1 2 TCG Transformation
1 3 VADL Intermediate Architecture Model (VIAM)
1 4 microprocessor design verification
1 5 Edge Coverage
1 6 test templates
1 7 event coverage
1 8 Control-Flow Integrity
1 9 coverage-guided test generation using Bayesian networks
1 10 interrupt delegation vulnerability
1 11 instruction histogram
1 12 vector instruction blacklisting
1 13 Write Integrity Testing
1 14 Architectural Unit
1 15 RISC-V CSR Compliance Testing
1 16 Micro-architecture Coverage Metrics
1 17 Verilog DPI
1 18 data memcheck
1 19 trace log
1 20 Processor Pipeline Forwarding Logic
1 21 RISC-V Processor Verification
1 22 instruction memcheck
1 23 CHERI-Concentrate
1 24 Sentry mechanism
1 25 vsetvli instruction generation
1 26 register writeback comparison
1 27 Privilege-Mode Transitions
1 28 riscv_instr_gen_config
1 29 Hardware Architecture Validity Rules
1 30 UART peripheral
1 31 shadow bitmap
1 32 register file initialization with random values
1 33 configuration instructions
1 34 linear capabilities
1 35 indirect capabilities
1 36 prefetching
1 37 RISC-V BOOM
1 38 ASIC acceleration
1 39 immediate value randomization
1 40 abstract-or-overapprox-vector hint
1 41 unsafe-custom-hint
1 42 Conformance Test Scenarios
1 43 Formal Microprocessor Model
1 44 Instruction Set Verification
1 45 Cryptographic Seed for Deterministic Randomness
1 46 Verilog Programming Interface (VPI)
1 47 AHB Verification IP
1 48 C++ reference model
1 49 White-Box RTL Model
1 50 DNF Masks Representation
1 51 UVM Register Abstraction Layer
1 52 RISC-V Toolchain
1 53 Board Support Package
1 54 Interrupt Agent
1 55 Memory Interface Agent
1 56 cycle-accurate simulation model
1 57 System On Chip
1 58 UVM Factory
1 59 Constraint Hierarchy
1 60 configuration register randomization
1 61 configuration register random coverage
1 62 Instruction Sequence State Space
1 63 RAW hazard avoidance constraint
1 64 State Update Function
1 65 Rocket Chip SoC Generator
1 66 Debug Transport Module
1 67 phase analysis
1 68 simulation points
1 69 trace comparison
1 70 domain reduction
1 71 RACE Solver
1 72 Weighted Distribution
1 73 BDD Solver
1 74 Implication Operator Constraints
1 75 Testcase Extraction Feature
1 76 Corner Case Biasing
1 77 data dependency hazards (RAW, WAR, WAW)
1 78 Dynamic Program Analysis
1 79 Memory Concurrency Testing
1 80 DLX instruction set
1 81 branch resolve unit
1 82 Unordered Floating-Point Reductions
1 83 vstart
1 84 core_ibex_base_test.sv
1 85 Speculative Instruction Issue
1 86 Directed-Random Verification
1 87 Corner Case Testing
1 88 Microcode Test Sequence
1 89 control flow vector
1 90 SystemVerilog Random Sequence Construct
1 91 gen_program_header
1 92 state-space explosion
1 93 Virtual Address Handling Bug
1 94 Transition Coverage
1 95 Illegal Bins
1 96 Sv39 Paging Mode
1 97 Integer ALU
1 98 Automated Random Test Generator
1 99 5-stage pipelined MIPS processor
1 100 hazard handling
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