Architectural Unit

Concept

An Architectural Unit (AU) is a processor architecture component or domain that can be verified independently, such as privileged or unprivileged parts of a RISC-V processor. ProcessorFuzz uses AUs to group CSR-transition coverage events so fuzzing can target individual units before exercising the processor as a whole.

First seen 5/29/2026

Last seen 5/29/2026

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WIKI

Definition

An Architectural Unit (AU) is a processor architecture domain that can be treated as a separately verifiable unit during processor verification. In the ProcessorFuzz context, AUs are used to organize control-and-status-register (CSR) transition coverage so that transitions belonging to different units can be explored independently.

Role in ProcessorFuzz

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ProcessorFuzz ← uses 90% 1e

ProcessorFuzz groups CSR transitions by Architectural Units to enable targeted verification.

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ProcessorFuzz USES Extracted graph relationship

CITATIONS

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[1] ProcessorFuzz uses Architectural Units as individually verifiable processor architecture scopes for CSR-transition coverage. ProcessorFuzz: Processor Fuzzing with Control and

[2] ProcessorFuzz groups CSR transitions of AUs and treats the groups as independent events to reduce the state space and improve exploration within each group. ProcessorFuzz: Processor Fuzzing with Control and

[3] AU-level grouping lets ProcessorFuzz generate tests targeted at individual AUs and supports verifying units before fuzzing the processor as a whole. ProcessorFuzz: Processor Fuzzing with Control and

[4] Privileged and unprivileged architectures in a RISC-V processor are cited as examples of AUs that can be verified individually by grouping transitions. ProcessorFuzz: Processor Fuzzing with Control and

[5] ProcessorFuzz stores CSR transitions in a transition map as tuples containing the instruction mnemonic and the CSR values before and after the transition. ProcessorFuzz: Processor Fuzzing with Control and