Definition
An Architectural Unit (AU) is a processor architecture domain that can be treated as a separately verifiable unit during processor verification. In the ProcessorFuzz context, AUs are used to organize control-and-status-register (CSR) transition coverage so that transitions belonging to different units can be explored independently.
Role in ProcessorFuzz
ProcessorFuzz allows designers to customize its CSR-transition coverage metric for verifying different AUs individually. It does this by grouping CSR transitions associated with AUs and treating each group as an independent event space. The stated purpose is to reduce the state space while improving exploration of CSR transitions within each group.
This grouping enables the fuzzer to generate tests targeted toward individual AUs, allowing verification engineers to check units as an initial verification step. The paper gives privileged and unprivileged architectures in a RISC-V processor as examples of units that can be verified separately by grouping transitions. The authors note that identifying and fixing bugs in each AU before fuzzing the whole processor can reduce overall verification effort.
Relationship to CSR-transition coverage
ProcessorFuzz monitors selected CSRs and records transitions caused by instruction execution. For AU-level verification, these transitions can be grouped by architectural unit. The same evidence describes a transition map entry as a tuple (Im, S0, S1), where Im is the instruction mnemonic and S0 and S1 are CSR values before and after the transition. AU grouping is applied to these CSR-transition events to make coverage more suitable for targeted verification.
Examples
In the cited RISC-V example, ProcessorFuzz can group transitions to verify:
- privileged architecture behavior; and
- unprivileged architecture behavior.
These examples illustrate that an AU is not necessarily a physical hardware block in the cited usage; it is an architectural verification scope used to structure coverage and testing.