vector instruction blacklisting

Concept

Vector instruction blacklisting is a verification practice in which selected vector instructions are temporarily excluded from generated tests while parts of a vector design are still under development. In the cited RISC-V vector accelerator verification flow, blacklisting was used with RISCV-DV-generated tests to keep functional tests usable at each iteration, then reduced gradually as design errors were fixed.

First seen 5/28/2026

Last seen 5/28/2026

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Definition

Vector instruction blacklisting is the temporary exclusion of selected vector instructions from generated verification tests. In the available evidence, it is described in the context of functional verification of a RISC-V vector processing unit, where many vector instructions were initially blacklisted because some design modules were still under development.

Use in RISC-V vector accelerator verification

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RELATIONSHIPS

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Functional Verification of a RISC-V Vector Accelerator ← uses 90% 1e

Vector instruction blacklisting is used to exclude unimplemented instructions during early verification phases.

riscv-dv ← implements 88% 1e

RISCV-DV supports the ability to blacklist vector instructions during test generation.

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

riscv-dv IMPLEMENTS Extracted graph relationship

CITATIONS

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[1] Vector instruction blacklisting is described as initially excluding many instructions from generated tests because design modules were still under development. source

[2] The purpose of the blacklist was to obtain functional tests at each verification iteration. source

[3] Instructions were gradually removed from the blacklist as errors were fixed, until all implemented instructions were enabled. source

[4] RISCV-DV generated random RISC-V assembly tests used to provide vector instructions to the VPU. source

[5] The verification effort adapted RISCV-DV with vector-related changes including vsetvli generation, element-width and vector-length changes, data-page initialization selection, constrained memory addresses, and RVV 0.7.1 adaptation. source