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vector instruction blacklisting

Concept WIKI v1 · 5/28/2026

Vector instruction blacklisting is a verification practice in which selected vector instructions are temporarily excluded from generated tests while parts of a vector design are still under development. In the cited RISC-V vector accelerator verification flow, blacklisting was used with RISCV-DV-generated tests to keep functional tests usable at each iteration, then reduced gradually as design errors were fixed.

Definition

Vector instruction blacklisting is the temporary exclusion of selected vector instructions from generated verification tests. In the available evidence, it is described in the context of functional verification of a RISC-V vector processing unit, where many vector instructions were initially blacklisted because some design modules were still under development.

Use in RISC-V vector accelerator verification

In the cited verification flow, the team used RISCV-DV to generate random RISC-V assembly tests that supplied vector instructions to the vector processing unit under test. Because the design was evolving, the generated tests initially excluded many instructions through a blacklist. This made it possible to obtain functional tests at each verification iteration rather than having tests dominated by instructions or modules that were not yet ready.

As more errors were fixed, instructions were gradually removed from the blacklist. The process continued until all implemented instructions were enabled in the generated tests.

Role in an iterative verification workflow

The evidence supports the following workflow:

  1. Generate random RISC-V assembly tests for the vector unit.
  2. Temporarily blacklist vector instructions associated with incomplete or error-prone design areas.
  3. Run functional tests at each design iteration.
  4. Fix design or verification errors.
  5. Gradually remove instructions from the blacklist.
  6. Eventually enable all implemented vector instructions.

Relationship to RISCV-DV adaptation

The same verification effort also modified RISCV-DV for its vector verification needs. Reported additions included generation of vsetvli instructions, support for changing element width and vector length, data-page initialization pattern selection, memory-address constraints to avoid exceptions, and adaptation to RVV 0.7.1. The blacklisting practice was used alongside these adaptations to keep generated tests practical while the vector design matured.

LINKED ENTITIES

2 links
Functional Verification of a RISC-V Vector Accelerator USES
riscv-dv IMPLEMENTS

CITATIONS

5 sources
5 citations
[1] Vector instruction blacklisting is described as initially excluding many instructions from generated tests because design modules were still under development. source
[2] The purpose of the blacklist was to obtain functional tests at each verification iteration. source
[3] Instructions were gradually removed from the blacklist as errors were fixed, until all implemented instructions were enabled. source
[4] RISCV-DV generated random RISC-V assembly tests used to provide vector instructions to the VPU. source
[5] The verification effort adapted RISCV-DV with vector-related changes including vsetvli generation, element-width and vector-length changes, data-page initialization selection, constrained memory addresses, and RVV 0.7.1 adaptation. source