Concept
Concept
4823 entities#
1 Benchmarks
3 2 rand_vec<T>
3 3 Pre-Silicon Fuzzing
3 4 Direct Tests
3 5 Bubble Sort Input Generation
3 6 Over-constraint Analysis
3 7 Design for Testability (DfT)
3 8 Marginal Defects
3 9 Inline Constraints
3 10 RISC-V compliance test suite
3 11 register update
3 12 XOR clauses
3 13 Natural Language Specification
3 14 Redundant State and Transition Elimination
3 15 AES Key Schedule
3 16 Bounded Model Check
3 17 Dynamic Constraint Management
3 18 Reachability Property
3 19 add.rm.ftz.sat.f32 C semantics
3 20 hardware emulation
3 21 Error Correction Code (ECC)
3 22 Valid Sequences (VS) test set
3 23 co-simulation methodology
3 24 LogGP model
3 25 Functional Safety
3 26 ARMv8 architecture
3 27 ARMv7 architecture
3 28 Invalid+Valid Sequences (IVS) test set
3 29 ARMv6 architecture
3 30 ARMv5 architecture
3 31 Verification Test Plan
3 32 Sandboxing
3 33 CodeCheckRunner
3 34 op_store_ri function
3 35 certification kit
3 36 Faulty Transition System
3 37 Concretization
3 38 Electronic System Level Design
3 39 differential testing engine
3 40 undefined behaviour
3 41 RISC-V software twin
3 42 BOOM Processor
3 43 Common Criteria EAL 7
3 44 Instruction Stream Generator
3 45 Code Fragment
3 46 Specification-Driven Directed Test Generation for Validation of Pipelined Processors
3 47 Test Controller
3 48 Ontology for Hardware Modeling
3 49 architectural certification tests
3 50 order semantics
3 51 LSTM
3 52 hardware-software communication
3 53 Load-Word Instruction Model
3 54 bi-variate linear constraints
3 55 non-deterministic events (NDEs)
3 56 Source Instrumentation
3 57 Per-Instruction Logging
3 58 ARM instruction encoding
3 59 ARM Architecture Specification Language (ASL)
3 60 hybrid symbolic execution
3 61 microarchitectural state clearing
3 62 verification database
3 63 linear feedback shift register
3 64 pseudo-random number generation
3 65 CPU state comparison
3 66 Cartesian product of mutation sets
3 67 multiplexer select signal
3 68 trace comparison
3 69 strip weight
3 70 Burn-In Test
3 71 D Programming Language
3 72 Privilege-Level Fault Handling
3 73 RISC-V Debug Specification
3 74 Sequence Length Scaling
3 75 memory corruption bugs
3 76 logic abstraction
3 77 Trace Abstraction
3 78 hardware security vulnerability
3 79 microarchitectural control flow (μCF)
3 80 execVAMP function
3 81 UNPREDICTABLE instruction behavior
3 82 run-time analysis
3 83 Cache Memory Modeling
3 84 non-intrusive emulation
3 85 declassification of legal flows
3 86 encoding symbol mutation
3 87 SPI peripheral
3 88 Instruction-by-Instruction Checking
3 89 Invalid+Valid Sequences test set
3 90 Module-Level Coverage Weighting
3 91 Bias Statements
3 92 Architectural Knowledge
3 93 Trusted Execution Environment (TEE)
3 94 Custom Instruction Streamer
3 95 Constructive Test Generation
3 96 Valid Sequences test set
3 97 CovGuidedTestsetGenerator
3 98 Information Flow Tracking (IFT)
3 99 Formal Property Verification (FPV)
3 100 AraRunner
3