ARM instruction encoding

Concept

An ARM instruction encoding specifies the binary layout of an ARM machine instruction, identifying which bit fields are constant and which are variable 'encoding symbols' that select registers, operands, and addressing modes. The ARM architecture defines 1,998 distinct instruction encodings across four instruction sets (A64, A32, T32, and T16), each with accompanying decoding and execution logic expressed in ARM's Architecture Specific Language (ASL).

First seen 6/7/2026

Last seen 6/7/2026

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ARM instruction encoding

Overview

An ARM instruction encoding is the binary pattern that defines a category of ARM machine instructions. Each encoding partitions the bits of an instruction word into fields that are fixed (constant) and fields that vary. The variable fields are called encoding symbols and determine operands such as registers, addressing modes, and immediate values ^[1]. A given functional instruction (e.g., STR (immediate)) typically corresponds to one or more of these encoding patterns, and the ARM architecture as a whole specifies 1,998 instruction encodings distributed across four instruction sets: A64, A32, T32, and T16 ^[2].

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Examiner parses ARM instruction encodings to extract symbols and generate test cases.

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[1] The ARM architecture defines 1,998 instruction encodings distributed across four instruction sets: A64, A32, T32, and T16. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[2] An ARM instruction encoding partitions its bits into constant fields and variable encoding symbols that select registers, operands, and addressing modes. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[3] In the STR (immediate) encoding, bits [31:20] and bit [7] are constant while Rn, Rt, P, U, W, and Imm8 are the encoding symbols. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[4] Each instruction encoding has decoding and execution logic expressed in ARM's Architecture Specific Language (ASL), which contains constraints on the encoding symbols that determine whether an instance is well-formed and which execution path is taken. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[5] The ARM architecture spans multiple revisions (ARMv5, ARMv6, ARMv7, ARMv8), 16-bit and 32-bit register widths, and mixed instruction modes including ARM, Thumb-1, and Thumb-2. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[6] Naively enumerating 32-bit ARM instruction streams would require 2^32 candidates, motivating an encoding-aware generation strategy. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[7] An encoding-aware generator produced 2,774,649 instruction streams covering all 1,998 ARM instruction encodings, versus 54.5% coverage for an equal number of random streams. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM