C++ reference model

Concept

A C++ reference model is the functional reference-calculation component used in a twin-based RISC-V verification framework. In the cited system, it executes vector instructions sequentially, represents co-processor memories with integer arrays, models addressing and bit-exact arithmetic/logic behavior, and serves as the comparison baseline for validating co-processor execution results.

First seen 6/1/2026

Last seen 6/1/2026

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C++ reference model

In the cited twin-based verification framework, the C++ reference model is the software implementation used for reference calculation of vector instructions alongside execution on the hardware co-processor. It is part of the RISC-V-side reference execution used to validate the co-processor's behavior.^[1]

Role in the verification flow

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RISC-V software twin ← uses 95% 1e

The RISC-V software twin is implemented in C++ as a reference model for V2PRO vector operations.

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CITATIONS

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[1] The C++ reference model is used as the reference calculation in a twin-based RISC-V verification flow. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[2] The reference calculation was implemented in C++ with the function behavior of each vector operation. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[3] The model processes vector instructions sequentially. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[4] The model iterates through vector units and vector lanes, and represents register files and local memories as integer arrays. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[5] The model implements vector operations with complex addressing parameters and bit-level exact masks for arithmetic and logic behavior. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[6] The chaining mechanism of neighbor vector lanes is simulated by sequential interleaving of element calculation and chaining-source selection. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[7] The co-processor emulation is functionally correct but coarse-grained, ignoring details such as pipeline execution and stall conditions. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[8] After execution on both twins, hardware results stored in external memory are compared against the reference memories, and mismatches cause verification failure with detailed reporting. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link