C++ reference model

In the cited twin-based verification framework, the C++ reference model is the software implementation used for reference calculation of vector instructions alongside execution on the hardware co-processor. It is part of the RISC-V-side reference execution used to validate the co-processor's behavior.^[1]

Role in the verification flow

After test sequences are generated, the vector instructions are executed on the V²PRO co-processor under control of the RISC-V core. In parallel, the same vector instructions are calculated by the RISC-V reference model. The results produced by hardware execution and by the reference memories are then compared; mismatches cause verification failure and trigger detailed reporting.^[2][3]

Implementation characteristics

The reference calculation was implemented in C++ with function-level behavior for each vector operation.^[4] According to the cited description, the model:

• processes vector instructions sequentially,^[5]
• iterates through the co-processor's vector units and vector lanes,^[6]
• realizes internal memories such as register files and local memories as integer arrays,^[7]
• handles complex addressing parameters in loops over vector operations,^[8]
• implements logic and arithmetic behavior with bit-level exact masks, including examples such as shifting and multiplication precision,^[9]
• simulates the chaining mechanism of neighbor vector lanes by sequential interleaving of vector-element calculation and chaining-source selection.^[10]

Modeling scope

The cited paper characterizes the co-processor emulation as functionally correct but coarse-grained. Specific hardware implementation details are intentionally omitted, including details such as a vector lane's pipeline execution and stall conditions.^[11]

Significance

Because the C++ reference model provides the reference execution against which hardware state is checked, it acts as the functional oracle in the framework's self-testing and validation process.^[3]

^[1]: Reference calculation is performed by the RISC-V reference model in the cited framework. ^[2]: The RISC-V controls execution of generated vector instruction sequences on the co-processor. ^[3]: After both twins execute the sequence, stored hardware results are compared with the reference memories. ^[4]: The reference calculation was implemented in C++. ^[5]: The model processes vector instructions sequentially. ^[6]: The V²PRO array is processed by iterating through vector units and vector lanes. ^[7]: Register files and local memories are realized by integer arrays. ^[8]: A loop processes vector operations with defined complex addressing parameters. ^[9]: Logic and arithmetic operations are implemented with corresponding bit-level exact masks. ^[10]: Neighbor-lane chaining is modeled by sequential interleaving of element calculation and chaining-source selection. ^[11]: The model is coarse-grained and ignores some hardware-specific execution details.