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configuration register randomization

Concept

Configuration register randomization is a test-generation technique in the described RISC-V/V²PRO self-testing framework in which special vector co-processor configuration registers are assigned random settings for each executed test sequence to increase coverage of configuration states and execution modes.

First seen 6/1/2026
Last seen 6/1/2026
Evidence 1 chunks
Wiki v1

WIKI

Configuration register randomization is used in the self-testing framework's architecture-specific extensions for vector instruction generation. In this context, the vector co-processor exposes several special configuration registers whose settings affect instruction behavior, and the framework emits random register configurations for each executed test sequence.[1][2]

Configurations covered

The evidence describes three configuration areas that are randomized:[1]

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RELATIONSHIPS

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random vector instruction generation ← uses 90% 1e
Random vector instruction generation applies configuration register randomization for each test sequence.

LINKED ENTITIES

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random vector instruction generation USES Extracted graph relationship

CITATIONS

5 sources
5 citations — click to expand
[1] Special configuration registers in the vector co-processor control the result shift in multiply vector instructions, the reset data source in multiply-and-accumulate vector instructions, and the reset condition of the accumulation register. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[2] For coverage of configuration register states and configured execution modes, random configurations are emitted for each executed test sequence. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[3] The configured execution modes explicitly include shift amounts for multiplication, reset modes for the multiply-accumulate vector instruction, and reset value configurations for multiply-accumulate vector instructions. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[4] To cope with these configuration-register features, corresponding code snippets were added to the RISC-V twin reference calculation. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[5] Configuration register randomization is described as part of an architecture-specific extension for vector instruction generation. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link