UVM Factory
ConceptThe UVM Factory is a factory design pattern mechanism in UVM that enables testbench objects or components to be substituted with derived types without changing the surrounding testbench structure or code.
First seen 5/27/2026
Last seen 5/28/2026
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Overview
The UVM Factory is a design-pattern mechanism within UVM used to substitute an object with a derived-type object without modifying the existing testbench structure or code. This substitution capability is provided through factory overrides, which may be applied by type or by instance.
Purpose
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1 connectionsThe UVM Factory is a design pattern component of UVM.
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[1] UVM provides a SystemVerilog class framework for building verification testbenches with components such as drivers, monitors, stimulus generators, and scoreboards. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The UVM Factory facilitates substituting an object with a derived-type object without modifying the testbench structure or code. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] UVM Factory override functionality can be applied by instance or by type. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] The UVM Factory is useful for altering sequence behavior or exchanging one version of a component with another. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] Successful component swapping through the UVM Factory requires polymorphic compatibility, including identical TLM interface handles and creation of required TLM objects by the replacement component. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] Using the UVM Factory requires adherence to specific coding conventions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi