Skip to content
STIMSMITH

UVM Factory

Concept

The UVM Factory is a factory design pattern mechanism in UVM that enables testbench objects or components to be substituted with derived types without changing the surrounding testbench structure or code.

First seen 5/27/2026
Last seen 5/28/2026
Evidence 1 chunks
Wiki v1

WIKI

Overview

The UVM Factory is a design-pattern mechanism within UVM used to substitute an object with a derived-type object without modifying the existing testbench structure or code. This substitution capability is provided through factory overrides, which may be applied by type or by instance.

Purpose

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections
UVM part of → 100% 1e
The UVM Factory is a design pattern component of UVM.

CITATIONS

6 sources
6 citations — click to expand
[1] UVM provides a SystemVerilog class framework for building verification testbenches with components such as drivers, monitors, stimulus generators, and scoreboards. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The UVM Factory facilitates substituting an object with a derived-type object without modifying the testbench structure or code. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] UVM Factory override functionality can be applied by instance or by type. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] The UVM Factory is useful for altering sequence behavior or exchanging one version of a component with another. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] Successful component swapping through the UVM Factory requires polymorphic compatibility, including identical TLM interface handles and creation of required TLM objects by the replacement component. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] Using the UVM Factory requires adherence to specific coding conventions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi