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UVM Factory

Concept WIKI v1 · 5/27/2026

The UVM Factory is a factory design pattern mechanism in UVM that enables testbench objects or components to be substituted with derived types without changing the surrounding testbench structure or code.

Overview

The UVM Factory is a design-pattern mechanism within UVM used to substitute an object with a derived-type object without modifying the existing testbench structure or code. This substitution capability is provided through factory overrides, which may be applied by type or by instance.

Purpose

The factory is used to introduce variation into a verification environment while preserving the testbench infrastructure. The cited source describes this as useful for changing sequence behavior or replacing one version of a component with another.

Override compatibility requirements

For a component swap to work correctly, the original and replacement components must be polymorphically compatible. The evidence specifically states that compatible components must have identical TLM interface handles and that the replacement component must create the required TLM objects.

Coding conventions

Use of the UVM Factory requires adherence to specific coding conventions. The evidence does not enumerate those conventions, but it states that following them is mandatory in order to leverage the factory mechanism.

Role in UVM

UVM is described as a SystemVerilog class framework for building verification testbenches, including components such as drivers, monitors, stimulus generators, and scoreboards. Within that object-oriented framework, the factory supports flexible substitution and extension of verification components and objects.

LINKED ENTITIES

1 links
UVM PART_OF

CITATIONS

6 sources
6 citations
[1] UVM provides a SystemVerilog class framework for building verification testbenches with components such as drivers, monitors, stimulus generators, and scoreboards. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The UVM Factory facilitates substituting an object with a derived-type object without modifying the testbench structure or code. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] UVM Factory override functionality can be applied by instance or by type. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] The UVM Factory is useful for altering sequence behavior or exchanging one version of a component with another. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] Successful component swapping through the UVM Factory requires polymorphic compatibility, including identical TLM interface handles and creation of required TLM objects by the replacement component. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] Using the UVM Factory requires adherence to specific coding conventions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi