Concept
Concept
2130 entities#
1 intra-instruction semantics
2 2 inter-instruction semantics
2 3 fuzzing memory
2 4 inter-test case scoring
2 5 Generative Pre-trained Transformer
2 6 auto-regressive language model
2 7 endianness vulnerability
2 8 opcode mutation
2 9 baremetal environment
2 10 test instructions
2 11 information flow tracking
2 12 Simulator-Based Coverage
2 13 FPU Operations
2 14 Memory Management in Program Generation
2 15 Cascade Python Implementation
2 16 Polymorphism
2 17 Memory Disambiguation
2 18 AMBA CHI Protocol
2 19 CSR (Control and Status Register)
2 20 epac-vpu-dv
2 21 protocol_base_class
2 22 Opcode Trojan
2 23 Self-Checking Testbench
2 24 Assembly Code Generation
2 25 CPU State Observation
2 26 Action Space
2 27 State Vector
2 28 Markov Decision Process
2 29 Replay Buffer
2 30 Prioritized Replay Buffer
2 31 Temporal Difference Error
2 32 Multi-Layer Perceptron
2 33 Policy
2 34 CVE2 Core
2 35 Open Bus Interface
2 36 Control Status Registers
2 37 IBM RISC System/6000
2 38 Synthetic Program Generation
2 39 Enumerate Construct
2 40 Genloop Construct
2 41 Genif Construct
2 42 Genmath Construct
2 43 Feature Definition Section
2 44 Hierarchical Code Composition
2 45 Compiler Testing
2 46 Stencil Computation
2 47 Task Graph
2 48 Dynamic Voltage and Frequency Scaling
2 49 GPU Kernel
2 50 microarchitectural verification
2 51 intra-instruction constraints
2 52 scenario constraints
2 53 order constraints
2 54 L1 cache miss
2 55 knob-based instruction generation
2 56 rand_intf class
2 57 factory pattern
2 58 arm_factory
2 59 simd_factory
2 60 ThunderX2
2 61 Genassert Construct
1 62 is_arith predicate
1 63 Memory Write Monitoring
1 64 Read-Modify-Write
1 65 run.py
1 66 Maximally Diverse Interpretations
1 67 Memory Array Modeling
1 68 Pipelined Wishbone Adapter
1 69 Verilog Abstract Syntax Tree
1 70 Jaccard Similarity Coefficient
1 71 is_load_store predicate
1 72 Debug Mode Support
1 73 Multiple Instruction Issue
1 74 debug request
1 75 VAMP SML executable model
1 76 bindSE operator
1 77 CSR-Transition Coverage Metric
1 78 interrupt
1 79 Micro-architectural Bugs
1 80 Genesys-Pro
1 81 Trap and Interrupt Handling
1 82 Side Channel Vulnerabilities
1 83 Processor State Exploration
1 84 Qwen2.5 LLM
1 85 Counterexample Generation
1 86 Byte-Pair Encoding
1 87 AUK-V-Aethia
1 88 Fedar F1
1 89 Risco-5
1 90 transformer architecture
1 91 Hornet
1 92 Baby-Risco-5
1 93 RVX
1 94 Kronos
1 95 RS5
1 96 Superscalar-RISC-V-CPU
1 97 Instruction Set Simulator
1 98 Privileged CSR
1 99 init_gpr
1 100 RV64IMAFDC
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