Concept
Concept
2103 entities#
1 Test Format Spec
2 2 Attributes YAML
2 3 Integer Linear Programming
2 4 Directed Acyclic Graph
2 5 Instruction Registry
2 6 capability compression
2 7 tagged memory
2 8 Task Graph
2 9 Instruction Level Parallelism
2 10 Dynamic Voltage and Frequency Scaling
2 11 Loop Unrolling
2 12 Graph Coloring
2 13 Non-overlapping Rectangles
2 14 Search Space Heuristics
2 15 Vector Register File
2 16 Pipelined Execution
2 17 global state space exploration
2 18 pipeline resource token manager
2 19 hardware-in-the-loop testing
2 20 data dependency stall
2 21 cache miss penalty
2 22 on-the-fly test generation
2 23 partially instantiated test program
2 24 Algorithm 1 TGen
2 25 test oracle
2 26 formal processor model
2 27 Stream Generation
2 28 Enumerated Types in Formal Modeling
2 29 Pseudo Memory Unit
2 30 FPGA Emulation
2 31 multiplier functional unit
2 32 Speculative Execution Vulnerabilities
2 33 Cross-Checking Execution Results
2 34 DIFUZZRTL Source Code
2 35 Load Store Cache
2 36 Dynamic Base Block Cache
2 37 auto-regression
2 38 RISC-V instruction generation
2 39 MCU testbench
2 40 RISCV-DV testbench
2 41 GPU Kernel
2 42 AES
2 43 KMAC
2 44 HMAC
2 45 RISC-V compliance test suite
2 46 Microarchitectural Observability
2 47 Side Channel
2 48 Microarchitectural Data Sampling
2 49 Return Stack Buffer
2 50 Pre-Silicon Testing
2 51 Microarchitectural Controllability
2 52 Swappable Region
2 53 Shadow Circuit
2 54 DejaVuzz Source Code
2 55 Architecture Verification Program
2 56 Virtual Coverage
2 57 Validation Function
2 58 Object-Oriented Database
2 59 microarchitectural verification
2 60 RISC Architecture
2 61 Depth-First Tree Traversal
2 62 Testing Knowledge Base
2 63 Address Translation
2 64 Floating Point Unit
2 65 Carry Look-Ahead Adder
2 66 Format
2 67 Page Fault
2 68 Test Generator Implementation in C
2 69 Instruction Mix (IMIX)
2 70 Branch Transition Rate (BTR)
2 71 Branch Misprediction Rate
2 72 Instruction Cache Miss Rate (ICMR)
2 73 Data Cache Miss Rate
2 74 Spatial Locality
2 75 Average Basic Block Size
2 76 Dependency Distance
2 77 Convex Hull
2 78 SPEC benchmarks
2 79 Strided Memory Access
2 80 Instruction Count
2 81 Over-fitting Prevention
2 82 Formal Property Verification
2 83 Formal Testbench
2 84 intra-instruction semantics
2 85 CISC Instruction Set
2 86 inter-instruction semantics
2 87 riscv_asm_program_gen
2 88 fuzzing memory
2 89 Bias Statements in Test Templates
2 90 Soft Constraints
2 91 Hardware-software leakage contracts
2 92 inter-test case scoring
2 93 write_reg macro
2 94 Multicore Parallelism
2 95 Opcode Generator
2 96 Instruction Statement
2 97 Ontology
2 98 processor data path verification
2 99 processor control path verification
2 100 Microarchitectural state divergence
2