Concept
Concept
4823 entities#
1 STM7 micro-controller
3 2 RISC-V Sail specification model
3 3 rand_vec<T>
3 4 VHDL
3 5 Bubble Sort Input Generation
3 6 SystemC
3 7 IDL
3 8 Branch Target Buffer (BTB)
3 9 Dynamic Constraint Management
3 10 Inline Constraints
3 11 Over-constraint Analysis
3 12 RISC-V compliance test suite
3 13 external interface unit
3 14 Natural Language Specification
3 15 DVT team
3 16 Electronic System Level Design
3 17 Invalid+Valid Sequences (IVS) test set
3 18 AES Key Schedule
3 19 Redundant State and Transition Elimination
3 20 Simulation Performance (MIPS)
3 21 CodeCheckRunner
3 22 RISC-V Vectors Extension
3 23 Completeness Analysis
3 24 mbind operator
3 25 Concretization
3 26 coverage-driven test generation
3 27 state-exception monad
3 28 structural hazards
3 29 Temporal Logic
3 30 Sandboxing
3 31 Reachability Property
3 32 data hazards
3 33 Instruction Set Model
3 34 decoder overlap checking
3 35 Instruction-Level Unit Testing
3 36 Faulty Transition System
3 37 add.rm.ftz.sat.f32 C semantics
3 38 functionality-based coverage metrics
3 39 Code Fragment
3 40 AV-Check
3 41 Python DV evaluation harness
3 42 Architectural Variable (AV)
3 43 undefined behaviour
3 44 Valid Sequences (VS) test set
3 45 Digital Signal Processing
3 46 TLM (Transaction Level Modeling)
3 47 ePMP
3 48 Per-Instruction Logging
3 49 Cumulative Global Constraint
3 50 Global Constraints
3 51 Very Large Instruction Word
3 52 Source Instrumentation
3 53 multiplexer select signal
3 54 EIT Architecture
3 55 Page Table Randomization
3 56 Pseudorandom Biased Generation
3 57 CSR check
3 58 fine-grained memory protection
3 59 logic abstraction
3 60 layered test bench architecture
3 61 Symbolic Simulation
3 62 declassification of legal flows
3 63 CovGuidedTestsetGenerator
3 64 debug visibility
3 65 RISC-V profiles
3 66 Module-Level Coverage Weighting
3 67 Coverage-Observer
3 68 microprocessor design verification
3 69 Valid Sequences test set
3 70 Invalid+Valid Sequences test set
3 71 hardware security vulnerability
3 72 Constructive Test Generation
3 73 gen_instr function
3 74 taint tracking
3 75 op_store_ri function
3 76 Operation State Machine (OSM)
3 77 Shift-Left Verification
3 78 microarchitectural control flow (μCF)
3 79 PTX instruction set
3 80 RDSmap
3 81 AraRunner
3 82 mutation-based instruction generation
3 83 single-instruction isolation
3 84 bare-metal software
3 85 trace file
3 86 CHERI Early Benchmarks
3 87 Conditional jump
3 88 Indirect jump
3 89 Instruction Fetch Matching
3 90 Service-Oriented Architecture
3 91 diagnostic database
3 92 memory operation stimulus
3 93 Instruction-Accurate Simulation
3 94 vsetvli instruction
3 95 Deep-state Prioritization (dfs)
3 96 Instruction Pointer
3 97 UICR
3 98 Over-approximated Pre-image Operator
3 99 Self-Consistency Universal Property
3 100 emulation
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