CISC Instruction Set

Concept

A CISC instruction set is evidenced here through Y86-64, a complex instruction set computer processor styled after Intel64. The cited material identifies typical CISC traits including variable-length instruction encodings, condition-code side effects, condition-code-controlled branches and moves, memory/register side effects in stack instructions, and stack-based procedure calls.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

A CISC instruction set refers to a complex instruction set computer style of instruction set. In the provided evidence, Y86-64 is described as a CISC processor styled after the Intel64 instruction set. [C1]

The same source also frames processor behavior through the Instruction Set Architecture (ISA): an ISA specifies the effect of each instruction on architectural state, including registers, the program counter, and memory, using a sequential model in which instructions execute in strict order. [C2]

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LINKED ENTITIES

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Instruction Set Architecture specification_context The evidence explains that an ISA describes each instruction's effect on architectural state, providing the specification context for instruction sets.

CITATIONS

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7 citations — click to expand

[1] Y86-64 is described as a complex instruction set computer processor styled after the Intel64 instruction set. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] An ISA describes the effect of each instruction on architectural state, including registers, the program counter, and memory, under a sequential execution model. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] Typical CISC features identified for Y86-64 include variable-length encodings, condition-code side effects, condition-code-controlled branching and moves, memory/register side effects in push and pop instructions, and stack-based procedure-call support. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] Y86-64 instruction encodings range from one to ten bytes and consist of a one-byte instruction specifier, possibly a one-byte register specifier, and possibly an eight-byte constant word. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] Y86-64 call pushes the return address onto the stack and jumps to the destination, while ret pops the return address from the stack and jumps to that location. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] Y86-64 function codes specify the ALU operation, jump condition, or conditional move condition. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] Y86-64 also has RISC-like simplifying features: arithmetic and logical instructions operate only on registers, addressing is simple base plus displacement, and instruction bit encodings use simple, consistent fields. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5