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CISC Instruction Set

Concept WIKI v1 · 5/26/2026

A CISC instruction set is evidenced here through Y86-64, a complex instruction set computer processor styled after Intel64. The cited material identifies typical CISC traits including variable-length instruction encodings, condition-code side effects, condition-code-controlled branches and moves, memory/register side effects in stack instructions, and stack-based procedure calls.

Overview

A CISC instruction set refers to a complex instruction set computer style of instruction set. In the provided evidence, Y86-64 is described as a CISC processor styled after the Intel64 instruction set. [C1]

The same source also frames processor behavior through the Instruction Set Architecture (ISA): an ISA specifies the effect of each instruction on architectural state, including registers, the program counter, and memory, using a sequential model in which instructions execute in strict order. [C2]

CISC traits shown by Y86-64

The evidence explicitly lists several Y86-64 properties as typical of CISC instruction sets: [C3]

  • Variable-length encodings: Y86-64 instruction encodings range from one to ten bytes. [C4]
  • Condition-code side effects: arithmetic and logical instructions set condition codes as a side effect. [C3]
  • Condition-code-driven control flow and moves: condition codes control conditional branching and conditional moves. [C3]
  • Instructions with multiple architectural effects: pushq and popq both operate on memory and alter register values as side effects. [C3]
  • Stack-based procedure calls: the procedure-call mechanism uses the stack to save the return pointer; call pushes the return address and jumps, while ret pops the return address and jumps to it. [C5]

Encoding structure

For Y86-64, an instruction consists of a one-byte instruction specifier, possibly a one-byte register specifier, and possibly an eight-byte constant word. The instruction table in the evidence includes examples such as halt, nop, register moves, immediate moves, memory moves, ALU operations, jumps, conditional moves, call, ret, pushq, and popq; it also notes an optional iaddq instruction. [C4]

Function codes distinguish variants of operation classes: they specify the ALU operation, the jump condition, or the conditional move condition. Examples listed include addq, subq, andq, xorq, conditional jumps such as jle, jl, je, jne, jge, and jg, and conditional moves such as cmovle, cmovl, cmove, cmovne, cmovge, and cmovg. [C6]

Boundary with RISC-like simplifications

The cited Y86-64 material also notes that Y86-64 has simplifying features commonly associated with RISC instruction sets: arithmetic and logical instructions operate only on register data, addressing is limited to simple base-plus-displacement forms, and instruction bit fields are simple and used consistently across multiple instructions. [C7]

This makes Y86-64 useful in the cited work as a compact, formally verified case study: it has CISC-like characteristics while retaining simplifications that make the processor designs and ISA model tractable for verification. [C1] [C7]

LINKED ENTITIES

1 links
Instruction Set Architecture specification_context

CITATIONS

7 sources
7 citations
[1] Y86-64 is described as a complex instruction set computer processor styled after the Intel64 instruction set. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] An ISA describes the effect of each instruction on architectural state, including registers, the program counter, and memory, under a sequential execution model. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] Typical CISC features identified for Y86-64 include variable-length encodings, condition-code side effects, condition-code-controlled branching and moves, memory/register side effects in push and pop instructions, and stack-based procedure-call support. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] Y86-64 instruction encodings range from one to ten bytes and consist of a one-byte instruction specifier, possibly a one-byte register specifier, and possibly an eight-byte constant word. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] Y86-64 call pushes the return address onto the stack and jumps to the destination, while ret pops the return address from the stack and jumps to that location. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[6] Y86-64 function codes specify the ALU operation, jump condition, or conditional move condition. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[7] Y86-64 also has RISC-like simplifying features: arithmetic and logical instructions operate only on registers, addressing is simple base plus displacement, and instruction bit encodings use simple, consistent fields. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5