AMBA CHI Protocol

Concept

The AMBA CHI (Coherent Hub Interface) protocol is used by the eProcessor EuroHPC vector accelerator to access memory directly, bypassing the scalar core. Within the eProcessor verification environment (eprocessor-vpu-dv), a CHI Agent emulates this interface to validate the accelerator's direct memory transactions and memory disambiguation behavior under a weak memory ordering model.

First seen 6/14/2026

Last seen 6/14/2026

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Overview

The AMBA CHI (Coherent Hub Interface) protocol is employed by the eProcessor EuroHPC project's vector accelerator as the on-chip fabric for accessing main memory directly from the accelerator, without needing to forward memory requests to the scalar core. This contrasts with designs (such as the European Processor Initiative accelerator) where memory traffic is mediated by the scalar core through the Open Vector Interface (OVI).

Role in the eProcessor Vector Accelerator

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NEIGHBORHOOD

3 nodes · 3 edges

graph · AMBA CHI Protocol · depth=1

RELATIONSHIPS

2 connections

eprocessor-vpu-dv ← implements 90% 1e

eprocessor-vpu-dv implements the AMBA CHI protocol for direct memory access.

eProcessor EuroHPC ← uses 90% 1e

The eProcessor project uses the AMBA CHI protocol for direct memory access.

LINKED ENTITIES

2 links

eProcessor EuroHPC USES The eProcessor EuroHPC project's vector accelerator accesses memory directly using the AMBA CHI protocol.

eprocessor-vpu-dv IMPLEMENTS Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] In eProcessor, memory is accessed directly by the vector unit using the AMBA CHI protocol, rather than through the scalar core as in EPI. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)

[2] Memory disambiguation metadata must be exchanged on the scalar core–accelerator interface to comply with the weak memory ordering model when both agents access memory. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)

[3] The eprocessor-vpu-dv verification environment includes a CHI Agent, a CHI Request Node, and a NOC Node to model the accelerator's AMBA CHI master port onto the coherent fabric. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)

[4] The scalar core–accelerator interface in eProcessor extends the base protocol class and carries the information required to detect and avoid memory aliasing between core and accelerator. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)