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AMBA CHI Protocol

Concept WIKI v1 · 6/14/2026

The AMBA CHI (Coherent Hub Interface) protocol is used by the eProcessor EuroHPC vector accelerator to access memory directly, bypassing the scalar core. Within the eProcessor verification environment (eprocessor-vpu-dv), a CHI Agent emulates this interface to validate the accelerator's direct memory transactions and memory disambiguation behavior under a weak memory ordering model.

Overview

The AMBA CHI (Coherent Hub Interface) protocol is employed by the eProcessor EuroHPC project's vector accelerator as the on-chip fabric for accessing main memory directly from the accelerator, without needing to forward memory requests to the scalar core. This contrasts with designs (such as the European Processor Initiative accelerator) where memory traffic is mediated by the scalar core through the Open Vector Interface (OVI).

Role in the eProcessor Vector Accelerator

In the eProcessor architecture, the vector unit is a memory-mapped master on the system fabric:

  • The accelerator issues read and write transactions to memory directly over an AMBA CHI interface.
  • Because both the scalar core and the accelerator can independently access memory, the scalar core–accelerator custom interface must additionally carry memory disambiguation information so that in-flight loads and stores from the two agents do not violate the weak memory ordering model required by the RISC-V vector (RVV) ISA.
  • Vector configuration CSRs (vsetvl, vsetvli, csrr, csrw, etc.) are handled inside the vector unit itself in eProcessor, rather than in the scalar core as is done in EPI, and CSR read/write instructions must still be transported through the protocol interface.

Use in the eProcessor Verification Environment (eprocessor-vpu-dv)

The eprocessor-vpu-dv project reuses the split, interface-agnostic UVM verification infrastructure originally built for the EPI vector accelerator, but specializes it for the eProcessor interface. The CHI side of the verification environment (see Figure 6 of the source paper) includes:

  • A CHI Agent, which encapsulates the CHI protocol traffic to/from the design under test (DUT).
  • A CHI Request Node, representing the accelerator's master port onto the CHI fabric.
  • A NOC (Network-on-Chip) Node, representing the rest of the coherent system that the accelerator talks to.

The CHI Agent is wired in alongside the custom core–accelerator interface monitor (which observes the memory-aliasing metadata) so that the scoreboard can compare observed memory operations against the Spike ISS reference model, validating both the CHI transactions and the disambiguation signalling.

Verification Strategy

The base verification infrastructure (shared between EPI and eProcessor projects) provides:

  • Random test generation against the DUT.
  • Co-simulation with the Spike ISA simulator as a golden reference model, which also performs memory reads/writes needed to mimic the scalar core's side of memory traffic.
  • Instruction-by-instruction result comparison between the DUT and Spike.
  • A continuous integration environment for regressions and coverage.

For eProcessor, additional Spike modifications were introduced to support FP8, FP16, and AI instructions, and to handle CSR semantics where the vector unit owns the configuration registers.

See Also

LINKED ENTITIES

2 links
eProcessor EuroHPC USES
eprocessor-vpu-dv IMPLEMENTS

CITATIONS

4 sources
4 citations
[1] In eProcessor, memory is accessed directly by the vector unit using the AMBA CHI protocol, rather than through the scalar core as in EPI. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)
[2] Memory disambiguation metadata must be exchanged on the scalar core–accelerator interface to comply with the weak memory ordering model when both agents access memory. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)
[3] The eprocessor-vpu-dv verification environment includes a CHI Agent, a CHI Request Node, and a NOC Node to model the accelerator's AMBA CHI master port onto the coherent fabric. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)
[4] The scalar core–accelerator interface in eProcessor extends the base protocol class and carries the information required to detect and avoid memory aliasing between core and accelerator. Reusable UVM verification environment for RISC-V vector accelerators (EPI and eProcessor)