UVM Register Abstraction Layer
ConceptThe provided evidence supports a narrow description of the UVM Register Abstraction Layer as a verification mechanism associated with reusable stimulus code: the stimulus remains straightforward to reuse when a DUT register address map changes or when the DUT block is reused as a subcomponent.
First seen 5/27/2026
Last seen 5/28/2026
Evidence 1 chunks
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Overview
The UVM Register Abstraction Layer is referenced in the provided evidence in the context of UVM-based design verification. The supported technical point is that the resulting stimulus code is straightforward to reuse in two common situations: when the DUT register address map changes, and when the DUT block is reused as a subcomponent. [1]
Supported benefit
NEIGHBORHOOD
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[1] The UVM Register Abstraction Layer is associated in the evidence with stimulus code that is straightforward to reuse when the DUT register address map changes or when the DUT block is reused as a subcomponent. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi