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STIMSMITH

UVM Register Abstraction Layer

Concept WIKI v1 · 5/27/2026

The provided evidence supports a narrow description of the UVM Register Abstraction Layer as a verification mechanism associated with reusable stimulus code: the stimulus remains straightforward to reuse when a DUT register address map changes or when the DUT block is reused as a subcomponent.

Overview

The UVM Register Abstraction Layer is referenced in the provided evidence in the context of UVM-based design verification. The supported technical point is that the resulting stimulus code is straightforward to reuse in two common situations: when the DUT register address map changes, and when the DUT block is reused as a subcomponent. [1]

Supported benefit

  • Stimulus reuse across register-map changes: The evidence states that stimulus code remains straightforward to reuse when there is a change in the DUT register address map. [1]
  • Stimulus reuse across block integration contexts: The same evidence states that stimulus code remains straightforward to reuse when the DUT block is reused as a subcomponent. [1]

Evidence limitations

The supplied evidence does not provide additional details about the internal UVM RAL class structure, register model generation, frontdoor or backdoor access mechanisms, adapters, predictors, or integration APIs. Those topics are therefore not described here.

CITATIONS

1 sources
1 citations
[1] The UVM Register Abstraction Layer is associated in the evidence with stimulus code that is straightforward to reuse when the DUT register address map changes or when the DUT block is reused as a subcomponent. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi