Concept
Concept
2087 entities#
1 register dependencies
2 2 Dhrystone benchmark
2 3 RISC-V Foundation
2 4 pipeline interlocks
2 5 Transaction-Level Model (TLM)
2 6 High-Level Synthesis (HLS)
2 7 Invariant
2 8 bfloat16
2 9 Sv48
2 10 Sv39
2 11 Regression Testing
2 12 algebraic data type
2 13 Vector Extensions
2 14 Hypervisor Extensions
2 15 Virtual Coverage
2 16 many-sorted logic
2 17 loop snippet
2 18 conditional branch snippet
2 19 Abstraction Function
2 20 cross-level testing
2 21 ISA instruction set architecture
2 22 MIPS ISA
2 23 CoreIR
2 24 Branch Target Buffer (BTB)
2 25 instruction generation algorithm
2 26 Register Reuse
2 27 Liveness Verification
2 28 Checkpoint Map
2 29 First Instruction Fetch Bug
2 30 RISC-V instruction corpus
2 31 StarCoder2 LLM
2 32 opcode distribution and weighting
2 33 self-equivalence with don't-cares
2 34 Sign Extension Bug
2 35 code-based test generation
2 36 instruction field randomization
2 37 agile verification
2 38 Constraint Block
2 39 Opcode Transaction Class
2 40 snippet
2 41 Instruction Transaction Class
2 42 Micro-Architectural Variables
2 43 Speculative Fetch Detection
2 44 straight-line instruction sequence
2 45 ELF File Execution
2 46 Operation Properties
2 47 Forwarding Structure Testing
2 48 Illegal Opcode Injection
2 49 Constraint Solving for Instruction Generation
2 50 Fetch and Commit Trace Merging
2 51 abstract specification
2 52 Instruction Fetch Interface Monitoring
2 53 Architectural Coverage
2 54 Lockup Bug Detection
2 55 Reorder Buffer Monitoring
2 56 Lock-Step Compare
2 57 rand_instr_test
2 58 RV32I Instruction Set
2 59 test controller
2 60 Instruction Group Cross-product Coverage Points
2 61 Garbage Collection
2 62 Object-Oriented Programming
2 63 SoCFPGA Co-emulation
2 64 inter-seed scheduling
2 65 feedback-driven generation
2 66 vector/hypervisor extensions
2 67 Return Address Stack (RAS)
2 68 Qwen LLM Family
2 69 Coverage-Guided Testing
2 70 Assertion-Based Testing
2 71 instruction fetch matching algorithm
2 72 Instruction Decode (ID) stage
2 73 generate_directed_instr_stream function
2 74 SPLASH-2 benchmarks
2 75 Coverage-guided Aging Counter
2 76 Reorder Buffer (ROB)
2 77 TLB operations
2 78 WARL (Write Any Read Legal)
2 79 Instruction Opcode Class Hierarchy
2 80 page table
2 81 Instruction Issue (IS) stage
2 82 fuzz testing
2 83 ISA checker
2 84 Assumption-based Pruning
2 85 vstart value
2 86 vmm_data
2 87 Seed Selection
2 88 data forwarding path testing
2 89 instruction blacklisting
2 90 illegal instruction trap
2 91 interrupt stimulus
2 92 DPI-C interface
2 93 Self-Compositional Framework
2 94 Program Counter (PC)
2 95 Side-Channel Security
2 96 Microarchitectural state divergence
2 97 regression suite
2 98 Random Test Input Generation
2 99 processor control path verification
2 100 processor data path verification
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