Instruction blacklisting

Concept

Instruction blacklisting is a verification control used to exclude selected instructions from generated tests while parts of a design are still incomplete or unstable. In the cited VPU verification environment, many instructions were initially blacklisted in adapted RISCV-DV test generation to keep regressions functional during development, and were later re-enabled gradually as implementation matured and errors were fixed.

First seen 6/1/2026

Last seen 6/1/2026

Evidence 2 chunks

Wiki v1

WIKI

Instruction blacklisting

Instruction blacklisting is the practice of preventing specific instructions from being generated or exercised during verification runs. In the cited vector processing unit (VPU) environment, this was used as a temporary mechanism while parts of the design were still under development.^[1]

Use in the cited verification flow

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riscv-dv ← uses 96% 1e

RISCV-DV supports instruction blacklisting to exclude unimplemented instructions from generated tests.

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CITATIONS

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3 citations — click to collapse

[1] In the cited VPU verification environment, many instructions were initially blacklisted from generated tests because some design modules were still in development, and the blacklist was gradually reduced as errors were fixed. source

[2] Some instructions were blacklisted because they were not implemented, which artificially reduced reported error counts during that phase. source

[3] After the RTL team fixed more errors and implemented missing features, they started whitelisting instructions, which increased the number of errors found as more functionality was exercised. source