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Instruction blacklisting

Concept WIKI v1 · 6/1/2026

Instruction blacklisting is a verification control used to exclude selected instructions from generated tests while parts of a design are still incomplete or unstable. In the cited VPU verification environment, many instructions were initially blacklisted in adapted RISCV-DV test generation to keep regressions functional during development, and were later re-enabled gradually as implementation matured and errors were fixed.

Instruction blacklisting

Instruction blacklisting is the practice of preventing specific instructions from being generated or exercised during verification runs. In the cited vector processing unit (VPU) environment, this was used as a temporary mechanism while parts of the design were still under development.[1]

Use in the cited verification flow

The reported environment adapted RISCV-DV to generate random RISC-V assembly tests for a VPU. Because some design modules were still being developed for most of the verification process, the team initially blacklisted many instructions from generated tests so that each iteration could still produce functional tests.[1]

This makes instruction blacklisting a test-generation control: rather than disabling the whole flow, the generator excludes instructions that are not yet implemented or are known to be problematic, allowing the rest of the regression suite to continue running.[1]

Lifecycle: blacklisting to re-enabling

As implementation progressed and a significant number of errors were fixed, the team gradually removed instructions from the blacklist until all implemented instructions were enabled again.[1]

A later description of the same effort states that some instructions were not implemented and therefore had to be blacklisted, which temporarily reduced the number of observed errors. After the RTL team fixed more errors and completed missing features, they began whitelisting instructions, which increased the number of errors found during that period because more functionality was being exercised.[2]

Practical effect on verification results

The evidence shows two important effects:

  1. Short-term stabilization of regressions. Blacklisting let the team keep running functional tests while portions of the design were incomplete.[1]
  2. Temporary distortion of error counts. Because unsupported instructions were excluded, blacklisting could make the number of reported errors appear lower than it would be with broader instruction coverage.[2]

Relationship to RISCV-DV

In the cited environment, instruction blacklisting was applied within an adapted RISCV-DV-based stimulus flow. The same source describes several RISCV-DV modifications and then explicitly notes that many instructions were initially blacklisted from generated tests.[1]

[1]: Citation c1 [2]: Citation c2

LINKED ENTITIES

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riscv-dv USES

CITATIONS

3 sources
3 citations
[1] In the cited VPU verification environment, many instructions were initially blacklisted from generated tests because some design modules were still in development, and the blacklist was gradually reduced as errors were fixed. source
[2] Some instructions were blacklisted because they were not implemented, which artificially reduced reported error counts during that phase. source
[3] After the RTL team fixed more errors and implemented missing features, they started whitelisting instructions, which increased the number of errors found as more functionality was exercised. source