Concept
Concept
2087 entities#
1 cohort output
2 2 Church-Turing thesis
2 3 General Purpose Registers (GPRs)
2 4 worker process ABI
2 5 Automatic Test Pattern Generation (ATPG)
2 6 instruction blacklisting
2 7 GPU Kernel
2 8 adversarial instruction sequence
2 9 Polymorphism
2 10 RVFI-DII Interface
2 11 mishegos worker
2 12 assembly program test input
2 13 Bias Statements in Test Templates
2 14 Base Instruction Class
2 15 Object-Oriented Database
2 16 Feature Definition Section
2 17 Non-Determinism Removal
2 18 RISC-V Scalar Cryptography Extensions (Zk*)
2 19 RISC-V Bit Manipulation Extensions (Zb*)
2 20 RISC-V Entropy Source Extension (Zkr)
2 21 CHERI-RISC-V
2 22 Machine Learning for Test Generation
2 23 rv64i
2 24 Verilog
2 25 Functional Reference Model
2 26 False Positives in Verification
2 27 XTheadMemIdx Extension
2 28 Majority Vote Oracle
2 29 Memory Disambiguation
2 30 code-based test generation
2 31 Performance Monitoring Counters (PMCs)
2 32 Formal Property Verification
2 33 AMBA CHI Protocol
2 34 Cache Coherence Conflicts
2 35 CSR (Control and Status Register)
2 36 Built-In Self-Test (BIST)
2 37 Formal Testbench
2 38 Floating-Point NaN
2 39 Fuzzing Payload
2 40 coverage state space
2 41 Stream Generation
2 42 SMT-based formal verification
2 43 fuzz testing
2 44 opcode distribution and weighting
2 45 program-based stimulus
2 46 bit vector stimulus
2 47 Depth-First Tree Traversal
2 48 Model-based Random Testing
2 49 processor data path verification
2 50 page table
2 51 Branch Scenario Generation
2 52 Abstract Syntax Tree
2 53 Open Bus Interface
2 54 Scenario Generator
2 55 ARM instruction set architecture
2 56 Branch History Table
2 57 Instruction Issue Unit
2 58 A64 instruction set
2 59 A32 instruction set
2 60 T32 instruction set
2 61 design under verification (DUV)
2 62 CSP/SMT Solver
2 63 T16 instruction set
2 64 Randomized Test Strategy
2 65 Design-Independent Verification
2 66 Instruction Group Coverage Points
2 67 SMV model checker
2 68 epac-vpu-dv
2 69 Default Data Capability
2 70 Validation Function
2 71 Constraint Statement
2 72 principle of least privilege
2 73 software compartmentalization
2 74 RISC-V instruction generation
2 75 Coverage Group Format
2 76 Test Format Spec
2 77 Attributes YAML
2 78 behavioral semantics
2 79 STREXH instruction
2 80 Processor State Level Mutation
2 81 floating point unit FPU
2 82 Convex Hull
2 83 APSR status register
2 84 Bias Statements for Expert Rule Activation
2 85 FlexNLP RTL
2 86 Formal Verification Methods
2 87 Integer Linear Programming
2 88 Checkpoint Map
2 89 PicoRV32 (Pico)
2 90 Directed Acyclic Graph
2 91 ExclusiveMonitorsPass function
2 92 emulator detection
2 93 capability compression
2 94 anti-emulation
2 95 tagged memory
2 96 gen_program
2 97 opcode category partitioning
2 98 anti-fuzzing
2 99 intra-instruction semantics
2 100 Instruction Level Parallelism
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