**False positives in verification** are reported verification issues that arise from the verification method or property formulation rather than from an intended design violation. In the cited processor-verification context, false positives are identified as a practical limitation of using a single **self-consistency universal property** for formal verification: although such a property reduces specification effort because it is design-independent, it can still produce false positives and suffer from scalability problems as the state space grows exponentially.[a5ab8596-f9a5-48c2-8d42-b71a993e3e54]

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