APSR Status Register

Concept

The APSR (Application Program Status Register) is the status register in the ARM architecture, capturing processor condition flags that are updated as a side effect of instruction execution. In differential testing frameworks such as Examiner, the APSR is treated as a first-class component of the CPU state so that emulators and real devices can be checked for behavioral consistency at the flag level.

First seen 6/7/2026

Last seen 6/7/2026

Evidence 2 chunks

Wiki v1

WIKI

APSR Status Register

Overview

In the ARM architecture, the APSR (Application Program Status Register) is the status register that records condition flags (such as N, Z, C, V, Q, GE, and IT/ICI state, depending on architecture variant) produced or consumed by arithmetic, logical, comparison, and other data-processing instructions. Together with the general-purpose registers, the program counter, and observable memory writes, the APSR is part of the architectural state that fully determines the visible effect of an executed instruction.

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

differential testing ← uses 100% 2e

The differential testing engine includes the APSR status register as part of the CPU state for comparison.

LINKED ENTITIES

1 links

differential testing USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] In the ARM architecture, the status register is named APSR. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[2] The CPU state is modeled as the tuple <PC, Reg, Mem, Sta>, where Sta is the status register (APSR in ARM). Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[3] The final CPU state extends the initial tuple with a signal/exception component: [PC, Reg, Mem, Sta, Sig]. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[4] An instruction stream is treated as inconsistent whenever CPU_F(E) != CPU_F(R), so any APSR divergence is flagged. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[5] For registers including the status register (APSR), Examiner pushes them on the stack and writes them into a file for inspection. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[6] Capstone is used to identify target memory addresses of write instructions so that only relevant memory cells are compared, rather than the full memory space. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[7] Examiner is implemented in 5,074 lines of Python, 220 lines of C, and 200 lines of ARM assembly, with inline assembly handling state setup and result dumping. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM

[8] Test cases are generated by parsing the ASL with regular expressions and using the Z3 SMT solver to solve constraints, including boundary and negated constraints, over encoding symbols to explore multiple execution paths. Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM