2026-07-26
5 items 184 entities 219 connections
Processed 35 entities and 40 relations.
constrained-random verification simulation-based functional verification uniform SAT witness generation almost-uniform generation approximate model counting hashing-based sampling r-wise independent hash functions XOR clauses independent support Boolean satisfiability CNF formula Markov Chain Monte Carlo sampling binary decision diagrams DPLL SAT solver Tseitin encoding bounded model checking RTL simulation UniGen UniWit PAWS XORSample' ApproxMC CryptoMiniSAT sharpSAT leapfrogging heuristic blocking clauses SMTLib benchmarks ISCAS89 circuits sampling variables Sabharwal Selman Bellare Sipser Chakraborty Ermon
Processed 66 entities and 83 relations.
RemembERR microprocessor errata design testing and validation triggers contexts observable effects errata classification scheme concrete classification level abstract classification level class classification level design simulation formal verification silicon testing random test input generation four-eyes manual classification software-assisted classification regular expression filtering power level transition testing emulation coverage metrics golden model bug heredity forward-latent errata backward-latent errata Model Specific Register Instruction Set Architecture workaround power state transition PCIe interaction reset signal machine check exception speculative memory operation page table walk cache line boundary atomic memory operation TLB flush nested page table translation virtual machine guest context debug feature floating-point instruction CPUID IOMMU access memory fence instruction memory-mapped element interaction SGX SMM Intel AMD ETH Zurich Flavien Solt Patrick Jattke Kaveh Razavi RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation Intel Core microprocessor AMD Zen microprocessor family RISC-V CVA-6 Meltdown Foreshadow RIDL ZombieLoad syntax highlighting engine bug transmission across design generations state explosion post-silicon testing RemembERR database
HeteroFuzz: Fuzz Testing to Detect Platform Dependent Divergence for Heterogeneous Applications
source →Processed 35 entities and 42 relations.
HeteroFuzz Fuzz Testing AFL High-Level Synthesis Platform-Dependent Divergence Accelerator Value Spectra Dynamic Probabilistic Mutations Selective Hardware Simulator Invocation Heterogeneous Computing FPGA CPU RTL Xilinx Vivado HLS LLVM Code Coverage HLS Synthesis Pragmas Kernel-Sensitive Inputs Static Backward Slicing Control Flow Graph Custom Bitwidth HLS Dataflow Directive University of California, Los Angeles Qian Zhang Jiyuan Wang Miryung Kim HeteroFuzz: Fuzz Testing to Detect Platform Dependent Divergence for Heterogeneous Applications Xilinx Amazon F1 HLS Loop Unrolling Pragma Seed Input Integer Overflow Memory Access Divergence FIFO Queue Differential Testing OpenCV
Processed 36 entities and 44 relations.
RCSG covergroup functional coverage constrained random stimulus generation mailbox associative array clocking block zero delay synchronization constraint coverpoint interface modport ROM randomize method conditional compilation testbench program block package RTL instruction format R-format instruction microprocessor verification RISC-V rom_aleatoria module RCSG_RISCV class covergroups_RISCV class estimulos program if_rom interface utilidades_verificacion package rom_aleatoria_tb module top_duv module instruction_box typedef Quartus vlog EDA Playground UVM