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Abstract Classification Level

Concept

The abstract classification level is the middle tier of a three-level errata classification scheme (concrete, abstract, and class) introduced in the RemembERR project. It represents a higher level of abstraction than the exact actions described in an erratum, sitting between the concrete action (e.g., 'the core resumes from the C6 power state') and the broad class (e.g., 'power management'). This level is crucial because design testing and validation tools must achieve generality to maximize coverage; considering only specific concrete actions (like transitions from the C6 power state) may miss unknown bugs that manifest when transitioning from other power states. The abstract level contributes to better generality while remaining more specific than the highest class level, enabling more general conclusions about bugs triggered by a particular trigger class.

First seen 7/26/2026
Last seen 7/26/2026
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Abstract Classification Level

Overview

The abstract classification level is one of the three tiers of the errata classification scheme used by the RemembERR project to classify microprocessor errata from Intel Core and AMD families (since 2008). The three levels, in increasing order of abstraction, are:

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RELATIONSHIPS

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RemembERR ← uses 95% 2e
RemembERR classifies entries at the abstract level to generalize triggers, contexts, and effects.
errata classification scheme part of → 95% 1e
The errata classification scheme has the abstract level as one of its parts.

CITATIONS

6 sources
6 citations — click to expand
[1] The classification scheme is composed of three levels: the concrete level, the abstract level, and the class level. Leveraging Microprocessor Errata for Design Testing and Validation
[2] The abstract level represents a slightly higher level of abstraction than the concrete level; e.g., 'a transition between core power states' is an abstract-level description of the concrete action 'the core resumes from the C6 power state'. Leveraging Microprocessor Errata for Design Testing and Validation
[3] The abstract level is crucial since design testing and validation tools must achieve generality to maximize coverage; considering only concrete transitions such as from the C6 power state may miss unknown bugs that only manifest when transitioning from other power states. Leveraging Microprocessor Errata for Design Testing and Validation
[4] The class level represents the highest level of abstraction (e.g., 'power management'), providing even more generality, better readability, and enabling more general conclusions about bugs triggered by a particular trigger class. Leveraging Microprocessor Errata for Design Testing and Validation
[5] RemembERR is a comprehensive annotated database of all errata of Intel Core and AMD microprocessor families since 2008; each entry is manually annotated with triggers, contexts, and observations at the concrete level and then further classified at the abstract and class levels of abstraction. Leveraging Microprocessor Errata for Design Testing and Validation
[6] Categories for triggers, contexts, and observable effects were defined iteratively by processing unique errata and merging identical ones, yielding 60 total categories across the classification dimensions. Leveraging Microprocessor Errata for Design Testing and Validation