High-Level Synthesis

Technique

First seen 7/26/2026

Last seen 7/26/2026

Evidence 6 chunks

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

5 connections

FPGA uses → 100% 2e

High-Level Synthesis automatically generates RTL for FPGA accelerators from C/C++ code.

HLS developers must insert synthesis directives and pragmas to achieve good quality results.

The paper discusses High-Level Synthesis as the mechanism for generating FPGA accelerators from C/C++ code.

RTL uses → 100% 1e

High-Level Synthesis generates RTL descriptions from C/C++ kernel code.

Xilinx Vivado HLS ← implements 100% 1e

Xilinx Vivado HLS is a tool that implements High-Level Synthesis for FPGA development.