Concept
Concept
2087 entities#
1 Weighted Random Instruction Selection
4 2 Instruction Pipeline Register
4 3 Bottom-Up Instruction Space Exploration
4 4 Peripheral Control Processor
4 5 Jump-Starting (Warm-Up Simulation)
4 6 model-based testing
4 7 Processor State Coverage
4 8 Post-Silicon Fuzzing
4 9 Scenario Generator
4 10 Program Counter Capability
4 11 PowerPC Processor Verification
4 12 Object-Oriented Verification
4 13 medeleg CSR
4 14 table mutator
4 15 x language
4 16 instret CSR
4 17 Pipeline Hazards
4 18 trap handling
4 19 self-test program
4 20 BlackParrot Core
4 21 Illegal Instruction Generation
4 22 remainder register
4 23 Bug Detection
4 24 program counter
4 25 Instruction Generator (InstrGen)
4 26 Refinement Map
4 27 ISA specification
4 28 Automated Design Inspection
4 29 Code Generator
4 30 UCB1 (Upper Confidence Bound) algorithm
4 31 security verification
4 32 Translation Buffer
4 33 Constraint Solver
4 34 Wishbone Interface
4 35 ELF Binary
4 36 pseudo-operations
3 37 RISC-V Formal Interface (RVFI)
3 38 processing element
3 39 exceptions in pipeline
3 40 Exception Handling Verification
3 41 state-exception monad
3 42 gen_test_data command
3 43 RV32IF
3 44 architecture formalization
3 45 Portable Stimulus
3 46 Self-Checking Tests
3 47 x86
3 48 bitvector theory
3 49 gen_test_cases command
3 50 parametric rewrite rules
3 51 coarse-grained reconfigurable array
3 52 instruction selection
3 53 Self-Composition Deviation (SCD)
3 54 In-process Fuzzing
3 55 test case validity
3 56 control hazards
3 57 ISA formal specification
3 58 LLM Configuration File Generator
3 59 Wishbone Bus Interface
3 60 mbind operator
3 61 Load/Store Byte and Halfword Operations
3 62 asynchronous interrupts
3 63 Simulation Performance (MIPS)
3 64 Completeness Analysis
3 65 Virtual Prototype (VP)
3 66 external interface verification
3 67 Function Return Protection
3 68 cache coherence verification
3 69 composite test actions
3 70 Bounded Model Check
3 71 hardware emulation
3 72 LogGP model
3 73 register update
3 74 ePMP
3 75 Chisel
3 76 ARMv8 architecture
3 77 op_store_ri function
3 78 ARMv5 architecture
3 79 CSR check
3 80 Pseudorandom Biased Generation
3 81 ARMv6 architecture
3 82 run-time analysis
3 83 differential testing engine
3 84 ARMv7 architecture
3 85 Branch History Table (BHT)
3 86 Symbolic Simulation
3 87 Execution Trace Comparison
3 88 AES-RTL (Round Implementation)
3 89 theorem proving
3 90 Data Forwarding
3 91 Specification-Driven Directed Test Generation for Validation of Pipelined Processors
3 92 hardware-software communication
3 93 Pipeline Flushing
3 94 Shift-Left Verification
3 95 GaussianBlur RTL
3 96 vsetvli instruction
3 97 UVM Monitor
3 98 diagnostic database
3 99 Micro-architectural Bug Detection
3 100 order semantics
3