Simulation Performance (MIPS)

Concept

Simulation performance in the cited ISS-generation evaluation is reported in MIPS, meaning million instructions per second. The evaluated generated C++ instruction-set simulators reached 7.0 MIPS on a small pipelined processor and 1.2 MIPS on an industrial DLX-based design, compared with 14.0 MIPS and 2.5 MIPS respectively for commercial just-in-time compiled simulators.

First seen 5/29/2026

Last seen 5/29/2026

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Definition

In the evaluated instruction-set simulator (ISS) context, MIPS is used as a throughput metric meaning million instructions per second. The paper reports average ISS execution rates in MIPS when comparing interpretive simulation, commercial just-in-time compiled simulation (JIT-CS), and ISS code generated from a complete formal property suite. [C1]

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← evaluates 100% 1e

The paper evaluates the generated ISS in terms of simulation performance in MIPS.

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CITATIONS

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[1] MIPS is used as million instructions per second in the ISS performance evaluation. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] For P1, the interpretive simulator achieved 0.22 MIPS, the commercial JIT-CS simulator achieved 14.0 MIPS, and the generated ISS achieved 7.0 MIPS, about 50% of the JIT-CS performance. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] For P2, the commercial JIT-CS simulator achieved 2.5 MIPS and the generated ISS achieved 1.2 MIPS; the paper describes this as comparable to modern custom-made instruction-set simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] The P1 test processor had 8 16-bit registers, an interrupt-return-vector register, a 5-stage pipeline, a simple data-memory interface, and 7 instructions. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] The P2 industrial design had 64 32-bit registers in multiple hardware contexts, a 7-stage pipeline, memory and bus interfaces, 88 DLX-based instructions, about 10,000 lines of VHDL, and a 2,000-line ITL property suite. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] The generated simulator used optimizations including native C++ types and operations where possible, optimized libraries for complex or large-vector operations, shared-expression and intermediate-result caching, and instruction-decode caching. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] The paper attributes the remaining speed advantage of custom JIT-CS simulators to commercial optimization and to generated properties reflecting hardware and pipeline effects that may be absent from high-level ISA descriptions. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[8] The paper concludes that a complete formally verified property suite can be used to generate a C++ ISS equivalent to the verified design by construction, with performance comparable to state-of-the-art commercial tools. Generating an Efficient Instruction Set Simulator from a Complete Property Suite