Concept
Concept
2087 entities#
1 Workload Characterization
5 2 Instruction Morphing
5 3 multiplexer toggle coverage
5 4 Seed Distance
5 5 Automatic Workload Generation
5 6 Synthetic Benchmark Generation
5 7 Instruction Instrumentation
5 8 Architecture Description Language
5 9 multiplexer
5 10 Declarative Architectural Specification
5 11 Constraint Satisfaction Problem (CSP)
5 12 Greybox Fuzzing
5 13 Taint Propagation
5 14 Transient Execution
5 15 Bluespec MCU RTL core
5 16 heuristic-based code generation
5 17 Address Expression
5 18 OpenRISC ISA
5 19 Testing Block
5 20 pipeline hazards templates
5 21 fence.i Instruction
5 22 Design Under Verification
5 23 Transaction Abstraction
5 24 UVM Coverage
5 25 Length Expression
5 26 Fuzzing Instruction Prevalence
5 27 resource EFSM
5 28 CSR Testing
5 29 UVM Sequences
5 30 RISC-V ISA tests
5 31 RTL model
5 32 Sequential Reference Model (SEQ)
5 33 Multi-bank Memory
5 34 RISC-V BOOM Core
5 35 Finite State Machine (FSM)
5 36 Interface Model
5 37 Instruction Execution Unit
5 38 XTheadVec Extension
5 39 Undocumented Instructions
5 40 State Coverage
5 41 Instruction Fetch Unit
5 42 model-based verification
5 43 Tandem Verification
5 44 Memory Interface
5 45 RTL verification
5 46 Property Suite
5 47 Endless Randomized Instruction Stream Generation
5 48 CPU Fuzzing
5 49 checkpoint
5 50 Ibex
5 51 C++ Instruction Set Simulator
5 52 CPU Bug Detection
5 53 DPI calls
5 54 functional processor description
5 55 temporal memory safety
5 56 RTL Fuzzing
5 57 Control Register
5 58 UVM scoreboard
4 59 ISA specification
4 60 Refinement Map
4 61 Wishbone Interface
4 62 trap handling
4 63 Automated Design Inspection
4 64 Illegal Instruction Generation
4 65 Code Generator
4 66 UVM agent
4 67 Instruction Generator (InstrGen)
4 68 Morpher Hardware Logic Block
4 69 State Synchronization
4 70 Bug Detection
4 71 Next State Function
4 72 Custom Benchmark
4 73 BlackParrot Core
4 74 basic_arithmetic_test
4 75 Execution Trace Generation
4 76 random test generation
4 77 Constrained-Random Testing
4 78 FIFO
4 79 Program Semantic Level Mutation
4 80 control-flow operations
4 81 Mutation-Based Testing
4 82 arithmetic operations
4 83 load and store operations
4 84 Term-Level Modeling
4 85 memory access (MMIO)
4 86 instruction class
4 87 opcode class
4 88 instruction commit
4 89 monitor unit
4 90 golden reference model (REF)
4 91 communication overhead
4 92 Bit-Vector Modeling
4 93 Memory Alignment Constraint
4 94 structural semantics
4 95 Implementation Differences
4 96 STR (immediate) instruction
4 97 Instruction Fetch (IF) unit
4 98 UNDEFINED instruction behavior
4 99 Physical Memory Protection (PMP)
4 100 Processor State Coverage
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